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path: root/src/mesa/drivers/dri/i965/brw_eu_emit.c
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* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-3675/+0
* i965: split EU defines to brw_eu_defines.hEmil Velikov2017-03-131-1/+1
* i965: Reduce cross-pollination between the DRI driver and compilerJason Ekstrand2017-03-011-1/+0
* i965: add assert to while_jumps_before_offset()Timothy Arceri2017-01-301-0/+1
* i965: Use UNUSED to silence unused variable (used in assert).Matt Turner2017-01-231-1/+1
* Revert "i965: Really don't emit Q or UQ moves on Gen < 8"Matt Turner2017-01-201-8/+0
* i965: Enable emitting Q and UQ instructions in the fs backendIan Romanick2017-01-201-1/+4
* i965: Really don't emit Q or UQ moves on Gen < 8Ian Romanick2017-01-201-0/+8
* i965: Replace reg_type_size[] with a function.Matt Turner2017-01-201-3/+53
* i965: Validate math instruction sources.Matt Turner2017-01-201-9/+0
* i965: Use W-typed immediate in brw_F32TO16().Matt Turner2017-01-201-1/+1
* i965: Don't change F->VF if dest type is DF.Matt Turner2017-01-201-1/+2
* i965: Use align1 mode for barrier messages.Kenneth Graunke2017-01-151-0/+3
* i965/fs: Expose arbitrary pull constant load sizes to the IR.Francisco Jerez2016-12-141-7/+8
* i965: Factor out oword block read and write message control calculation.Francisco Jerez2016-12-141-12/+2
* i965/fs: Switch to the constant cache for uniform pull constants.Francisco Jerez2016-12-141-3/+2
* i965: Let the caller of brw_set_dp_write/read_message control the target cache.Francisco Jerez2016-12-141-39/+30
* i965: Emit proper NOPs.Matt Turner2016-12-061-4/+2
* i965: fix unused variable warning in gen7_block_read_scratch()Timothy Arceri2016-10-051-2/+1
* i965/fs: Take Dispatch/Vector mask into account in FIND_LIVE_CHANNELJason Ekstrand2016-09-211-9/+30
* intel: Rename brw_get_device_name/info to gen_get_device_name/infoJason Ekstrand2016-09-031-1/+1
* intel: s/brw_device_info/gen_device_info/Jason Ekstrand2016-09-031-71/+71
* i965: Pass start_offset to brw_set_uip_jip().Matt Turner2016-08-311-11/+3
* i965/eu: Add codegen support for the Gen9+ render target read message.Francisco Jerez2016-08-251-0/+28
* i965/eu: Take into account the target cache argument in brw_set_dp_read_message.Francisco Jerez2016-08-251-2/+13
* i965/eu: set DF imm value to the source of DIMSamuel Iglesias Gonsálvez2016-07-141-1/+2
* i965: enable the emission of the DIM instructionSamuel Iglesias Gonsálvez2016-07-141-0/+1
* Revert "i965/fs: Allow scalar source regions on SNB math instructions."Francisco Jerez2016-06-031-4/+2
* i965/eu: use simd8 when exec_size != EXECUTE_16Alejandro Piñeiro2016-06-021-2/+2
* i965/fs: Allow scalar source regions on SNB math instructions.Francisco Jerez2016-05-311-2/+4
* i965/ir: Make BROADCAST emit an unmasked single-channel move.Francisco Jerez2016-05-271-3/+9
* i965/fs: Allow specifying arbitrary quarter control to FIND_LIVE_CHANNEL.Francisco Jerez2016-05-271-7/+12
* i965/fs: Allow specifying arbitrary execution sizes up to 32 to FIND_LIVE_CHA...Francisco Jerez2016-05-271-8/+17
* i965/fs: Implement scratch reads and writes of 4 GRFs at a time.Francisco Jerez2016-05-271-18/+13
* i965/eu: Fix Gen7+ DP scratch message size calculation on Gen7.Francisco Jerez2016-05-271-1/+4
* i965/eu: Set execution size explicitly for memory fence send message.Francisco Jerez2016-05-271-4/+7
* i965/eu: Consider QtrCtrl 3Q-4Q in typed surface message descriptor setup.Francisco Jerez2016-05-271-6/+6
* i965/fs: Clean up remaining uses of dispatch_width in the generator.Francisco Jerez2016-05-271-2/+1
* i965/eu: Use current exec size instead of p->compressed in surface message ge...Francisco Jerez2016-05-271-6/+8
* i965/eu: Stop using p->compressed to specify the exec size of control flow in...Francisco Jerez2016-05-271-13/+11
* i965/eu: Fix a bunch of compression control bugs in the generator.Francisco Jerez2016-05-271-9/+8
* i965: Mark fallthrough in switch statement.Matt Turner2016-05-251-0/+1
* i965: Fix JIP to skip over sibling do...while loops.Kenneth Graunke2016-05-161-1/+6
* i965: Make a "does this while jump before our instruction?" helper.Kenneth Graunke2016-05-161-4/+12
* i965: two-argument instructions can only use 32-bit immediatesIago Toral Quiroga2016-05-101-0/+2
* i965/eu: add support for DF immediatesConnor Abbott2016-05-101-7/+21
* i965/eu: Allow 3-src float ops with doublesTopi Pohjolainen2016-05-101-6/+18
* i965: fix invalid memory writeMarc-André Lureau2016-03-211-1/+1
* i965: Skip execution size adjustment for instructions of width 4Iago Toral Quiroga2016-03-171-1/+13
* i965: set correct execsize for MOVS with a width of 4 in brw_find_live_channelIago Toral Quiroga2016-03-171-0/+3
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