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path: root/src/mesa/drivers/dri/i965/brw_eu.h
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* i965: Add support for register spilling.Eric Anholt2010-10-211-6/+9
* i965: Add EU emit support for gen6's new IF instruction with comparison.Eric Anholt2010-10-191-0/+2
* i965: Add support for ir_unop_round_even via the RNDE instruction.Kenneth Graunke2010-10-141-0/+1
* i965: Correctly emit the RNDZ instruction.Kenneth Graunke2010-10-141-2/+7
* i965: Add support for POW in gen6 FS.Eric Anholt2010-09-281-0/+6
* i965: Make brw_CONT and brw_BREAK take the pop count.Eric Anholt2010-08-301-2/+2
* i965: Also use the SIMD8 FB writes for SIMD8 mode on non-SNB.Eric Anholt2010-08-201-0/+1
* i965: Add AccWrCtl support on Sandybridge.Zhenyu Wang2010-08-201-0/+1
* i965: Don't set the swizzle on an immediate value in the VS.Eric Anholt2010-08-181-0/+4
* i965: Fix reversed naming of the operations in compute-to-mrf optimization.Eric Anholt2010-07-261-1/+1
* i965: Move the GRF-to-MRF optimizations to brw_optimize.c.Eric Anholt2010-07-261-0/+2
* i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.Eric Anholt2010-07-211-3/+0
* i965: Support relative addressed VS constant reads using the appropriate msg.Eric Anholt2010-07-211-0/+6
* i965: Add 'wait' instruction supportZhenyu Wang2010-07-081-0/+16
* mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul2010-06-101-1/+1
* i965: Remove constant or ignored-by-hw args from FF sync message setup.Eric Anholt2010-05-181-6/+1
* i965: Fix up VS DP4 sequences to avoid dependency control.Eric Anholt2010-03-121-0/+5
* i965: Use the PLN instruction when possible in interpolation.Eric Anholt2010-03-101-0/+1
* i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt2009-11-061-5/+5
* i965: add support for new chipsetsXiang, Haihao2009-07-131-1/+16
* i965: use BRW_MAX_GRF, BRW_MAX_MRFBrian Paul2009-06-301-2/+3
* i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger2009-06-261-3/+0
* i965: increase BRW_EU_MAX_INSNBrian Paul2009-05-121-1/+1
* i915: fix broken indirect constant buffer readsBrian Paul2009-04-171-0/+1
* i965: implement relative addressing for VS constant buffer readsBrian Paul2009-04-161-0/+1
* i965: fix VS constant buffer readsBrian Paul2009-04-141-3/+0
* i965: checkpoint commit: VS constant buffersBrian Paul2009-04-141-1/+10
* i965: added brw_same_reg()Brian Paul2009-04-031-0/+7
* i965: added new brw_dp_READ_4() functionBrian Paul2009-04-031-0/+7
* i965: more register number assertionsmesa_20090313Brian Paul2009-03-131-0/+7
* i965: bump up BRW_EU_MAX_INSNBrian Paul2009-03-061-1/+1
* i965: rewrite the code for handling shader subroutine callsBrian Paul2009-02-131-0/+18
* i965: implement OPCODE_TRUNC (round toward zero) on vertex path.Brian Paul2009-01-051-0/+1
* i965: comments, clean-ups, re-order some functionsBrian Paul2009-01-011-34/+54
* i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong2008-11-051-0/+6
* i965: support destination horiz strides in align1 access mode.Gary Wong2008-10-311-1/+1
* replace __inline and __inline__ with INLINE macroBrian Paul2008-06-211-63/+63
* [i965] short immediate values must be replicated to both halves of the dwordKeith Packard2008-04-251-2/+2
* i965: new integrated graphics chipset supportXiang, Haihao2008-01-291-1/+2
* fix fd.o bug #13847Zou Nan hai2007-12-291-0/+5
* fragment shader function call fix, gl_FragCoord fixZou Nan hai2007-09-301-0/+5
* support continue, fix conditionalZou Nan hai2007-09-291-0/+1
* support branch and loop in pixel shaderZou Nan hai2007-06-211-2/+6
* Initial 965 GLSL supportZou Nan hai2007-04-121-1/+2
* Update DRI drivers for new glsl compiler.Brian2007-02-231-1/+1
* i965: Avoid branch instructions while in single program flow mode.Eric Anholt2007-01-061-0/+1
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+863
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