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path: root/src/mesa/drivers/dri/i965/brw_disasm.c
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* i965: Don't print WE_normal in disassembly.Kenneth Graunke2014-07-231-1/+1
* i965/disasm: Don't disassemble the URB complete field on Broadwell.Kenneth Graunke2014-07-211-2/+4
* i965/disasm: add support for pixel interpolator messagesChris Forbes2014-07-131-0/+17
* i965/disasm: Disassemble indirect sends more properlyChris Forbes2014-07-121-162/+174
* i965/disasm: Fix disassembly of the any16h/all16h predicates.Kenneth Graunke2014-07-081-1/+1
* i965/disasm: Improve render target write message disassembly.Kenneth Graunke2014-06-301-30/+47
* i965/disasm: Rename msg_target to SFID.Kenneth Graunke2014-06-301-12/+8
* i965/disasm: Fix typo in RT UNORM write message.Kenneth Graunke2014-06-301-1/+1
* i965/disasm: Use Gen6+ SFID case labels.Kenneth Graunke2014-06-301-2/+4
* i965/disasm: "Handle" Gen8+ HF/DF immediate cases.Kenneth Graunke2014-06-301-0/+7
* i965/disasm: Cut piles of duplicate swizzle printing.Kenneth Graunke2014-06-301-89/+26
* i965/disasm: Properly decode negate source modifiers on Broadwell.Kenneth Graunke2014-06-301-4/+49
* i965/disasm: Improve disassembly of atomic messages on Haswell+.Kenneth Graunke2014-06-301-7/+21
* i965/disasm: Actually disassemble Gen7+ URB opcodes.Kenneth Graunke2014-06-301-3/+19
* i965/disasm: Decode Broadwell's invm/rsqrtm math functions.Kenneth Graunke2014-06-301-0/+2
* i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.Kenneth Graunke2014-06-301-2/+3
* i965/disasm: Properly disassemble all32h/any32h align1 predicates.Kenneth Graunke2014-06-301-11/+13
* i965/disasm: Mark ELSE as having UIP on Gen8+.Kenneth Graunke2014-06-301-0/+1
* i965/disasm: Properly disassemble jump targets on Gen4-5.Kenneth Graunke2014-06-301-0/+15
* i965/disasm: Improve disassembly of jump targets on Gen6+.Kenneth Graunke2014-06-301-18/+41
* i965/disasm: Add support for new Gen8+ register types.Kenneth Graunke2014-06-301-16/+24
* i965: Restyle brw_disasm.c.Kenneth Graunke2014-06-301-1234/+1231
* i965/disasm: Create an "opcode" temporary.Kenneth Graunke2014-06-301-31/+30
* i965/disasm: Eliminate opcode pointer.Kenneth Graunke2014-06-301-8/+7
* i965: Disassemble all of DP write message control bits on Gen6.Kenneth Graunke2014-06-261-1/+1
* i965: Replace 'struct brw_instruction' with 'brw_inst'.Matt Turner2014-06-261-19/+11
* i965: Convert brw_disasm.c to the new brw_inst API.Matt Turner2014-06-261-341/+316
* i965: Pass brw rather than gen to brw_disassemble_inst().Matt Turner2014-06-261-27/+27
* i965/disasm: Mark three_source_reg_encoding[] static.Matt Turner2014-06-171-1/+1
* i965: Don't include mtypes.h in brw_disasm.cKristian Høgsberg2014-06-091-2/+0
* i965: Rename brw_disasm/gen8_disassemble to brw/gen8_disassemble_inst.Kenneth Graunke2014-05-181-1/+3
* i965/disasm: Align send instruction meta-information with dst.Matt Turner2014-05-151-0/+1
* i965/disasm: Disassemble the compaction control bit.Matt Turner2014-05-151-1/+8
* i965/disasm: Fix s/xoo/xor/ typo.Matt Turner2014-04-221-1/+1
* i965/disasm: Remove tables with obvious mappings.Matt Turner2014-04-221-10/+1
* i965: Fill in a bunch of gen7/hsw data cache-related disasm.Eric Anholt2014-04-111-7/+103
* i965: Fix register types in dump_instructions(), again.Kenneth Graunke2014-03-141-1/+1
* i965: Disassemble 3 src instructions' rep_ctrl field.Matt Turner2014-03-101-3/+12
* i965: Disassemble 3-src operands widths' correctly.Matt Turner2014-03-101-3/+3
* i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values.Kenneth Graunke2013-12-201-8/+8
* i965: Decode three-source register types directly.Kenneth Graunke2013-12-201-25/+14
* i965: Disassemble UV types, not UB types.Kenneth Graunke2013-12-201-2/+2
* i965: Don't use GL types in files shared with intel-gpu-tools.Kenneth Graunke2013-12-051-41/+41
* i965: Externalize conditional_modifier for use in dump_instruction().Matt Turner2013-12-041-1/+1
* i965: Externalize reg_encoding for use in dump_instruction().Matt Turner2013-12-041-1/+1
* i965: Fix disassembled names of BFI1 and BFI2 instructions.Matt Turner2013-11-201-2/+2
* i965: Generate code for ir_binop_carry and ir_binop_borrow.Matt Turner2013-10-071-0/+2
* i965: Add support for emitting and disassembling bit instructions.Matt Turner2013-05-061-0/+7
* i965: Print the correct dst and shared-src types for 3-src instructions.Matt Turner2013-05-061-4/+22
* i965: Remove traces of nonexistent TAN math function.Matt Turner2013-04-241-1/+1