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path: root/src/mesa/drivers/dri/i965/brw_defines.h
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* Revert "intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM"Kenneth Graunke2019-09-231-4/+0
* intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WMAnuj Phogat2019-09-111-0/+4
* i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.Rafael Antognolli2019-08-121-0/+4
* i965/gen9: Optimize slice and subslice load balancing behavior.Francisco Jerez2019-08-121-0/+5
* intel/perf: move get_query_data into gen_perfMark Janes2019-08-071-12/+0
* intel/perf: move perf-related constants to common locationMark Janes2019-08-071-14/+0
* i965: disable repacking for compression for applicable genDongwon Kim2019-07-081-0/+1
* Revert "i965/icl: Add WA_2204188704 to disable pixel shader panic dispatch"Anuj Phogat2019-06-281-4/+0
* i965: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-181-0/+1
* i965/icl: Add WA_2204188704 to disable pixel shader panic dispatchAnuj Phogat2019-03-191-0/+4
* intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITSJason Ekstrand2019-01-291-1/+1
* i965/gen10+: Enable object level preemption.Rafael Antognolli2018-12-141-0/+5
* i965/icl: Set use full ways in L3CNTLREGAnuj Phogat2018-11-261-0/+1
* i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREGAnuj Phogat2018-11-011-0/+1
* i965/icl: Set Enabled Texel Offset Precision Fix bitAnuj Phogat2018-09-211-0/+4
* i965/icl: Allow headerless sampler messages for pre-emptable contextsAnuj Phogat2018-08-211-0/+4
* i965: perf: snapshot RPSTAT registerLionel Landwerlin2018-04-231-0/+12
* intel: Apply Geminilake "Barrier Mode" workaround.Kenneth Graunke2018-01-091-0/+5
* i965: Move PIPE_CONTROL defines and prototypes to brw_pipe_control.h.Kenneth Graunke2017-12-041-43/+0
* i965: Remove DWord length from MI_FLUSH_DW definitionAnuj Phogat2017-11-171-1/+1
* i965/gen10: Implement Wa3DStateModeAnuj Phogat2017-11-031-0/+2
* i965/gen10: Enable float blend optimizationAnuj Phogat2017-11-031-0/+3
* i965/gen10: Implement WaSampleOffsetIZ workaroundAnuj Phogat2017-11-031-0/+1
* i965: Set "Subslice Hashing Mode" to 16x16 on Apollolake.Kenneth Graunke2017-08-021-0/+7
* i965: Switch to absolute addressing for constant buffer 0.Kenneth Graunke2017-07-131-0/+6
* i965: Add Gen8+ INTEL_performance_query supportRobert Bragg2017-06-271-0/+1
* i965: Set the "Float Blend Optimization Enable" bit on Gen9+.Kenneth Graunke2017-05-301-0/+1
* i965: Move clip program compilation to the compilerJason Ekstrand2017-05-261-7/+0
* i965: Move SF compilation to the compilerJason Ekstrand2017-05-261-2/+0
* i965: Move MOCS macros to brw_context.h.Rafael Antognolli2017-05-031-42/+0
* i965: Delete tile resource mode codeAnuj Phogat2017-03-271-9/+0
* intel: fix compiler buildIago Toral Quiroga2017-03-131-8/+0
* i965: split EU defines to brw_eu_defines.hEmil Velikov2017-03-131-1188/+0
* i965: move brw_define.h ifndef guard to the topEmil Velikov2017-03-131-3/+3
* i965: remove unused macros from brw_defines.hEmil Velikov2017-03-131-19/+1
* i965: Delete vestiges of resource streamer code.Kenneth Graunke2017-03-061-52/+0
* i965: Replace BRW_SURFACEFORMAT_* with ISL_FORMAT_*.Kenneth Graunke2017-03-021-247/+0
* i965: Reduce cross-pollination between the DRI driver and compilerJason Ekstrand2017-03-011-0/+2
* i965: Get rid of BRW_PRIM_OFFSETJason Ekstrand2017-03-011-8/+0
* i965/vec4: Rename DF to/from F generator opcodesIago Toral Quiroga2017-01-031-2/+2
* i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodesIago Toral Quiroga2017-01-031-0/+2
* i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodesIago Toral Quiroga2017-01-031-0/+2
* i965/vec4: add double/float conversion pseudo-opcodesIago Toral Quiroga2017-01-031-0/+2
* i965/fs: Remove the FS_OPCODE_SET_SIMD4X2_OFFSET virtual opcode.Francisco Jerez2016-12-141-1/+0
* i965: Factor out oword block read and write message control calculation.Francisco Jerez2016-12-141-0/+6
* treewide: s/comparitor/comparator/Ilia Mirkin2016-12-121-1/+1
* i965: enable INTEL_conservative_rasterization on Gen9+Lionel Landwerlin2016-12-071-0/+1
* i965/fs: Refactor handling of constant tg4 offsetsJason Ekstrand2016-11-291-1/+1
* i965: Use 3DSTATE_CLIP's User Clip Distance Enable bitmask on Gen8+.Kenneth Graunke2016-11-231-0/+1
* i965/ir: Update several stale comments.Francisco Jerez2016-09-141-1/+1
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