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path: root/src/mesa/drivers/dri/i965/brw_defines.h
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* i965/gen6+: Add support for edge flags.Eric Anholt2012-08-091-0/+1
* i965/msaa: Add CMS-related sampler messages to brw_defines.h.Paul Berry2012-07-111-0/+2
* i965/fs: Add FS_OPCODE_MOV_DISPATCH_TO_FLAGS to fragment shader backend.Paul Berry2012-07-021-0/+1
* i965/msaa: Adapt clip setup for centroid noperspective interpolation.Paul Berry2012-06-251-0/+4
* i965/msaa: Add defines for Gen7.Paul Berry2012-05-251-0/+5
* i965/blorp: Implement proper texel fetch messages for Gen7.Paul Berry2012-05-251-0/+1
* i965: add flag to enable cut_indexJordan Justen2012-05-231-0/+2
* i965/gen6+: Add support for fast depth clears.Eric Anholt2012-05-231-1/+3
* i965/gen6: Initial implementation of MSAA.Paul Berry2012-05-151-0/+7
* i965: Set "Shader Channel Select" fields in Haswell's SURFACE_STATE.Kenneth Graunke2012-03-301-0/+8
* i965: Fill in Sample Mask in Haswell's 3DSTATE_PS.Kenneth Graunke2012-03-301-0/+2
* i965: Set "Stencil Buffer Enable" bit on Haswell.Kenneth Graunke2012-03-301-0/+1
* i965: Set Line Stipple enable bit in 3DSTATE_SF for Haswell.Kenneth Graunke2012-03-301-0/+2
* i965: Update max VS/PS threads shift offsets for Haswell.Kenneth Graunke2012-03-301-1/+3
* i965: Add support for the MAD opcode on gen6+.Eric Anholt2012-02-101-0/+1
* i965: fix inverted point sprite origin when rendering to FBOYuanhan Liu2012-01-281-0/+1
* i965: Fix misnamed GEN7_WM_DEPTH_RESOLVEChad Versace2012-01-101-1/+1
* i965/gen7: Add register definitions for GL_EXT_transform_feedback.Eric Anholt2011-12-231-2/+71
* i965 gen6: Initial implementation of transform feedback.Paul Berry2011-12-201-0/+6
* i965: Add missing SIMD4x2 sample_l_c message #defines.Kenneth Graunke2011-12-191-0/+1
* i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB.Kenneth Graunke2011-12-181-6/+8
* i965 gen6: Implement pass-through GS for transform feedback.Paul Berry2011-12-071-0/+3
* i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.Paul Berry2011-12-071-4/+4
* i965/gen6: Set vertical alignment in SURFACE_STATE batchChad Versace2011-11-221-4/+5
* i965/gen6+: Rename GEN6_CLIP_BARYCENTRIC_ENABLE.Paul Berry2011-10-271-1/+1
* i965/gen6+: Parameterize barycentric interpolation modes.Paul Berry2011-10-271-6/+12
* i965: Add more #defines for Gen6+ 3DSTATE_GS fields.Kenneth Graunke2011-10-251-0/+8
* i965: setup address rounding enable bitsYuanhan Liu2011-10-191-0/+7
* i965: Rename BRW_MESSAGE_TARGET_* to BRW_SFID_* and document them.Kenneth Graunke2011-10-181-12/+26
* i965: Use Ivybridge's "Legacy Data Port" for reads/writes.Kenneth Graunke2011-10-181-0/+5
* i965: Replace incorrect use of GLboolean with enum brw_compression.Kenneth Graunke2011-10-111-3/+5
* i965/fs: Implement integer quotient and remainder math operations.Kenneth Graunke2011-10-021-0/+2
* i965: Fix incorrect maximum PS thread count shift on Ivybridge.Kenneth Graunke2011-09-261-1/+1
* i965/fs: Implement texelFetch() on Ironlake and Sandybridge.Kenneth Graunke2011-09-191-0/+2
* i965/vs: Add support for pull constant loads for uniform arrays.Eric Anholt2011-08-301-0/+1
* i965: Implement textureSize (TXS) on Gen4.Kenneth Graunke2011-08-231-1/+0
* i965/fs: Implement textureSize (TXS) on Gen5+.Kenneth Graunke2011-08-231-0/+2
* i965/vs: Move virtual GRFs with array accesses to them to scratch space.Eric Anholt2011-08-161-0/+2
* i965: Start adding the VS visitor and codegen.Eric Anholt2011-08-161-0/+2
* i965: Rename math FS_OPCODE_* to SHADER_OPCODE_*.Eric Anholt2011-08-161-8/+8
* i965: Create a shared enum for hardware and compiler-internal opcodes.Eric Anholt2011-08-161-52/+82
* i965: Rename CMD_VF_STATISTICS_(965|GM45) to include "3DSTATE".Kenneth Graunke2011-07-181-2/+2
* i965: Rename CMD_VERTEX_(BUFFER|ELEMENT) to 3DSTATE_VERTEX_...S.Kenneth Graunke2011-07-181-2/+2
* i965: Convert system instruction pointer to OUT_BATCH style.Kenneth Graunke2011-07-071-1/+1
* i965: Switch brw_state_dump to using bitshifting for surface state.Eric Anholt2011-05-311-0/+4
* i965: Replace struct with bit shifting for WM pull constant surfaces.Eric Anholt2011-05-311-0/+1
* i965: Replace struct with bit shifting for WM render target surfaces.Eric Anholt2011-05-311-0/+5
* i965: Add defines for surface state setup using bitfield shifting.Eric Anholt2011-05-311-1/+33
* i965: Set Address Modify Enable in VERTEX_BUFFER on Ivybridge.Kenneth Graunke2011-05-171-0/+1
* i965: Emit 3DPRIMITIVE Ivybridge-style.Kenneth Graunke2011-05-171-0/+3
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