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* i965/fs: Statically allocate the reg_sets at context initialization.Eric Anholt2012-10-171-0/+2
| | | | | | | Now that we've replaced all the variable settings other than reg_width, it's easy to hang on to this (the expensive part of setting up the allocator). Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Remove the EmitNVTempInitialization shader compiler option.Kenneth Graunke2012-10-161-1/+0
| | | | | | | Nobody uses it anymore. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Reduce maximum GL_ARB_fragment_program instruction count to 1024.Eric Anholt2012-10-081-4/+4
| | | | | | | | | I don't know of any programs that would need more than this. The larger programs I've seen have neared 100 instructions. This prevent excessive runtimes of automatic tests that attempt to test up to the exposed maximums (like fp-long-alu). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: brwInitVtbl needs to know the chipset generationIan Romanick2012-09-281-0/+5
| | | | | | Fixes major regressions since de958de. Signed-off-by: Ian Romanick <[email protected]>
* i965: Don't free the intel_context structure when intelCreateContext fails.Ian Romanick2012-09-281-3/+2
| | | | | | | | | | | | | intelDestroyContext will eventually be called, and it will clean things up. The call to brwInitVtbl is moved earlier so that intelDestroyContext can call the device-specific destructor. This also makes the code look more like the i915 code. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301
* mesa: s/FREE/free/Brian Paul2012-09-011-1/+1
| | | | | | | v2: replace instances in dri/common/ dirs Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Allow creation of OpenGL 3.1 contextsIan Romanick2012-08-291-0/+19
| | | | | | | | v2: Fix API_OPENGL_CORE handling when TEXTURE_FLOAT_ENABLED is not defined. Based on review feedback from Eric Anholt. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set context flagsIan Romanick2012-08-291-0/+8
| | | | Signed-off-by: Ian Romanick <[email protected]>
* i965: Disable the swrast context setup on GL 3.1 core.Eric Anholt2012-08-281-1/+3
| | | | | | | | | | | | | | I've reviewed the code, and the swrast callsites remaining are all in drawpixels/copypixels/bitmap/accum, or _swrast_BlitFramebuffer that shouldn't be hit. A piglit run with the context setup disabled on legacy GL and GLES2 showed regressions only in the copypixels and drawpixels tests. If the context type is forced, this reduces the shader_runner maximum heap size for glsl-algebraic-add-add-1.shader_test from 15,137,496b to 4,165,376b. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen6+: Add support for GL_ARB_timer_query.Eric Anholt2012-08-261-0/+2
| | | | | | Needs updated libdrm. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Validate API and version in brwCreateContextIan Romanick2012-08-131-3/+37
| | | | | | | v2: Use base-10 for versions like gl_context::Version. Suggested by Ken. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7: Reduce GT1 WM thread count according to updated BSpec.Eric Anholt2012-07-271-1/+1
| | | | | | Acked-by: Kenneth Graunke <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=52382
* intel: increase wm thread number to 80 on gen6 GT2Zou Nan hai2012-07-271-5/+1
| | | | | | | | | | | | | It seems reset is not required for setting the max_wm_threads to 80 on gen6 GT2. Increases performance in the Counter-Strike: Source video stress test by 7.18% (n=5). Signed-off-by: Zou Nan hai <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Matt Turner <[email protected]> Acked-by: Eric Anholt <[email protected]>
* i965/msaa: Switch on 8x MSAA for Gen7.Paul Berry2012-07-241-1/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Remove comment about falsely claiming to support MSAA.Paul Berry2012-07-241-5/+0
| | | | | | Gen6+ hardware now supports MSAA properly. Reviewed-by: Chad Versace <[email protected]>
* i965/gen7: Increase the WM threads to hardware limits.Eric Anholt2012-07-201-1/+1
| | | | | | | | | | | | This thread count is only supposed to be enabled when "WIZ Hashing Disable in GT_MODE register enabled." I've always been confused whether that means the bit in the register should be 1 or 0. For my IVB GT2's register 0x7008 value of 0x0, this appears to work fine. Improves l4d2 performance at 640x480 by 0.88 +/- 0.11% (n=88). Improves performance with rasterization at 1280x1024 by 1.45% +/- 0.36% (n=6). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add hardware context support.Kenneth Graunke2012-07-101-0/+1
| | | | | | | | | | | With fixes and updates from Ben Widawsky and comments from Paul Berry. v2: Use drm_intel_gem_context_destroy to destroy hardware context; remove useless initialization of hw_ctx, both suggested by Eric. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965/msaa: Fix centroid interpolation of unlit pixels.Paul Berry2012-07-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | From the Ivy Bridge PRM, Vol 2 Part 1 p280-281 (3DSTATE_WM: Barycentric Interpolation Mode): "Errata: When Centroid Barycentric mode is required, HW may produce incorrect interpolation results when a 2X2 pixels have unlit pixels." To work around this problem, after doing centroid interpolation, we replace the centroid-interpolated values for unlit pixels with non-centroid-interpolated values (which are interpolated at pixel centers). This produces correct rendering at the expense of a slight increase in shader execution time. I've conditioned the workaround with a runtime flag (brw->needs_unlit_centroid_workaround) in the hopes that we won't need it in future chip generations. Fixes piglit tests "EXT_framebuffer_multisample/interpolation {2,4} {centroid-deriv,centroid-deriv-disabled}". All MSAA interpolation tests pass now. Reviewed-by: Eric Anholt <[email protected]>
* mesa: rename MaxTransformFeedbackSeparateAttribs to MaxTransformFeedbackBuffersMarek Olšák2012-06-281-1/+1
| | | | | | | | | | | | This is a cleanup for ARB_transform_feedback3, where GL_MAX_TRANSFORM_FEEDBACK_BUFFERS is introduced for interleaved attribs and has the same meaning as GL_MAX_.._SEPARATE_ATTRIBS for separate attribs. Also, the maximum number of TFB buffers is reduced from 32 to 4, which makes this patch useful even without the extension. I don't know of any hardware which can do more than 4. Reviewed-by: Brian Paul <[email protected]>
* i965: add flag to enable cut_indexJordan Justen2012-05-231-0/+1
| | | | | | | | | When brw->prim_restart.enable_cut_index is set, the cut index will be enabled when uploading index_buffer commands. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: create code path to handle primitive restart in hardwareJordan Justen2012-05-231-0/+2
| | | | | | | | | | | | | | For newer hardware we disable the VBO module's software handling of primitive restart. We now handle primitive restarts in brw_handle_primitive_restart. The initial version of brw_handle_primitive_restart simply calls vbo_sw_primitive_restart, and therefore still uses the VBO module software primitive restart support. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/gen6+: Add support for GL_ARB_blend_func_extended.Eric Anholt2012-05-231-0/+1
| | | | | | | v2: Add support for gen6, and don't turn it on if blending is disabled. (fixes GPU hang), and note it in docs/GL3.txt Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rewrite the HiZ opChad Versace2012-02-071-55/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HiZ op was implemented as a meta-op. This patch reimplements it by emitting a special HiZ batch. This fixes several known bugs, and likely a lot of undiscovered ones too. ==== Why the HiZ meta-op needed to die ==== The HiZ op was implemented as a meta-op, which caused lots of trouble. All other meta-ops occur as a result of some GL call (for example, glClear and glGenerateMipmap), but the HiZ meta-op was special. It was called in places that Mesa (in particular, the vbo and swrast modules) did not expect---and were not prepared for---state changes to occur (for example: glDraw; glCallList; within glBegin/End blocks; and within swrast_prepare_render as a result of intel_miptree_map). In an attempt to work around these unexpected state changes, I added two hooks in i965: - A hook for glDraw, located in brw_predraw_resolve_buffers (which is called in the glDraw path). This hook detected if a predraw resolve meta-op had occurred, and would hackishly repropagate some GL state if necessary. This ensured that the meta-op state changes would not intefere with the vbo module's subsequent execution of glDraw. - A hook for glBegin, implemented by brwPrepareExecBegin. This hook resolved all buffers before entering a glBegin/End block, thus preventing an infinitely recurring call to vbo_exec_FlushVertices. The vbo module calls vbo_exec_FlushVertices to flush its vertex queue in response to GL state changes. Unfortunately, these hooks were not sufficient. The meta-op state changes still interacted badly with glPopAttrib (as discovered in bug 44927) and with swrast rendering (as discovered by debugging gen6's swrast fallback for glBitmap). I expect there are more undiscovered bugs. Rather than play whack-a-mole in a minefield, the sane approach is to replace the HiZ meta-op with something safer. ==== How it was killed ==== This patch consists of several logical components: 1. Rewrite the HiZ op by replacing function gen6_resolve_slice with gen6_hiz_exec and gen7_hiz_exec. The new functions do not call a meta-op, but instead manually construct and emit a batch to "draw" the HiZ op's rectangle primitive. The new functions alter no GL state. 2. Add fields to brw_context::hiz for the new HiZ op. 3. Emit a workaround flush when toggling 3DSTATE_VS.VsFunctionEnable. 4. Kill all dead HiZ code: - the function gen6_resolve_slice - the dirty flag BRW_NEW_HIZ - the dead fields in brw_context::hiz - the state packet manipulation triggered by the now removed brw_context::hiz::op - the meta-op workaround in brw_predraw_resolve_buffers (discussed above) - the meta-op workaround brwPrepareExecBegin (discussed above) Note: This is a candidate for the 8.0 branch. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43327 Reported-by: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44927 Reported-by: [email protected] Signed-off-by: Chad Versace <[email protected]>
* i965: Add a driconf option to force GLSL extension behavior to "warn".Eric Anholt2012-01-301-0/+2
| | | | | | | | | This can be used to work around broken application behavior, like in Unigine where it attempts to use texture arrays without declaring either "#extension GL_EXT_texture_array : enable" or "#version 130". NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6/GT1: Increase max_vs_entries to 256.Paul Berry2012-01-251-1/+1
| | | | | | | | | | Previously, max_vs_entries was set to 128 for GT1, and 256 for GT2, based on the PRM (see Vol2, part1, p28). However, Bspec section 1.6.5 indicates that the maximum number of VS entries is 256 for GT1. No piglit regressions on GT1. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove the INTEL_OLD_VS option.Kenneth Graunke2012-01-181-8/+2
| | | | | | | | | | | | | | | Now that we no longer generate Mesa IR from GLSL IR, it's impossible to use the old vertex shader backend for GLSL programs. There's simply no Mesa IR to codegen from. Any attempt to do so would result in immediate GPU hangs, presumably due to the driver uploading an empty program with no EOT message. NOTE: This is a candidate for the 8.0 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Eugeni Dodonov <[email protected]>
* i965: Claim to support 4 multisamples on gen6+.Eric Anholt2012-01-101-0/+8
| | | | | | | | We're not quite ready to actually support it in the implementation, but at least this allows GL 3.0 API-reliant applications to hopefully run successfully, though they won't get multisampling. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Increase the number of array texture levels to the hardware limit.Eric Anholt2012-01-101-5/+6
| | | | | | | | | | The EXT_texture_array required only 64, but GL 3.0 required 256. Since we're already exposing values that can get us way beyond our ability to map the single object directly, go ahead and expose all the way to hardware limits. Tested with new piglit EXT_texture_array/maxlayers on gen7. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7: Flush the batch between transform feedbacks.Eric Anholt2012-01-061-3/+10
| | | | | | | | | | We need the kernel to reset our pointers to 0 in between. Note that the initialization of function pointer had to move to after InitContext since we didn't have intel->gen set up yet. Fixes piglit EXT_transform_feedback/immediate-reuse Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Implement bounds checking for transform feedback output.Kenneth Graunke2011-12-201-0/+1
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Flush pipeline on EndTransformFeedback.Paul Berry2011-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | A common use case for transform feedback is to perform one draw operation that writes transform feedback output to a buffer, followed by a second draw operation that consumes that buffer as vertex input. Since vertex input is consumed at an earlier pipeline stage than writing transform feedback output, we need to flush the pipeline to ensure that the transform feedback output is completely written before the data is consumed. In an ideal world, we would do some dependency tracking, so that we would only flush the pipeline if the next draw call was about to consume data generated by a previous draw call in the same batch. However, since we don't have that sort of dependency tracking infrastructure right now, we just unconditionally flush the buffer every time glEndTransformFeedback() is called. This will cause a performance hit compared to the ideal case (since we will sometimes flush the pipeline unnecessarily), but fortunately the performance hit will be confined to circumstances where transform feedback is in use. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965 gen6: Initial implementation of transform feedback.Paul Berry2011-12-201-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic transform feedback capability for Gen6 hardware. This consists of several related pieces of functionality: (1) In gen6_sol.c, we set up binding table entries for use by transform feedback. We use one binding table entry per transform feedback varying (this allows us to avoid doing pointer arithmetic in the shader, since we can set up the binding table entries with the appropriate offsets and surface pitches to place each varying at the correct address). (2) In brw_context.c, we advertise the hardware capabilities, which are as follows: MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64 MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4 MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16 OpenGL 3.0 requires these values to be at least 64, 4, and 4, respectively. The reason we advertise a larger value than required for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already set aside 64 binding table entries, so we might as well make them all available in both separate attribs and interleaved modes. (3) We set aside a single SVBI ("streamed vertex buffer index") for use by transform feedback. The hardware supports four independent SVBI's, but we only need one, since vertices are added to all transform feedback buffers at the same rate. Note: at the moment this index is reset to 0 only when the driver is initialized. It needs to be reset to 0 whenever BeginTransformFeedback() is called, and otherwise preserved. (4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader program to output transform feedback data as a side effect. (5) In gen6_gs_state.c, we configure the geometry shader stage to handle the SVBI pointer correctly. Note: ordering of vertices is not yet correct for triangle strips (alternate triangles are improperly oriented). This will be addressed in a future patch. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Advertise our vertex shader texture units.Kenneth Graunke2011-12-191-1/+1
| | | | | | | | | | | | | Previously, we advertised 0 VS texture units. Now that we have proper support for using the sampling engine in the VS, we can advertise 16, which is conveniently the number required for OpenGL 3.0. v2: Enable on Gen4. I hacked up my tests to not use flat ivec varyings and they pass. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965 gen6: Allocate URB space for GSPaul Berry2011-12-071-0/+1
| | | | | | | | | | | | | | When the GS is not in use, the entire URB space is available for the VS. When the GS is in use, we split the URB space 50/50. The 50/50 split is probably not optimal--we'll probably want tune this for performance in a future patch. For example, in most situations, it's probably worth allocating more than 50% of the space to the VS, since VS space is used for vertex caching. But for now this is good enough. Based on previous work by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set the maximum number of GS URB entries on Sandybridge.Kenneth Graunke2011-12-071-0/+2
| | | | | | | | | | | We never filled this in before because we didn't care. I'm skeptical these are correct; my sources indicate that both the VS and GS # of entries are 256 on both GT1 and GT2. I'm also loathe to change it and break stuff. Reviewed-by: Paul Berry <[email protected]>
* i965: Don't perform the precompile on fragment shaders by default.Eric Anholt2011-11-301-0/+1
| | | | | | | | | | | | | | | | It is useful to have this option for shader-db, and it was also good at the time where we were rejecting shaders due to various internal limits we hadn't supported yet. However, at this point the precompile step takes extra time (since not all NOS is known at link time) and spews misleading debug in the common case of debugging a real app. This is left in place for VS, where we still have a couple of codegen failure paths that result in link failure through precompile. Those need to be fixed. shader-db can still get at the debug info it wants using "shader_precompile=true" driconf option. Long term, we can probably build a good-enough app for shader-db to trigger real codegen.
* i965: Use the surface format table to determine render target supportedness.Eric Anholt2011-11-221-0/+2
| | | | | | | | | | | | | This moves any chipset-dependent logic we want for render target format choices to init time as well. There is still logic left at state update for SRGB handling, where format choices change based on GL state. The brw_render_target_supported() function should now return correct results, instead of relying on the limited results from intel_span_supports_format() to avoid lying about FBO completeness. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Prevent recursive calls to FLUSH_VERTICES [v2]Chad Versace2011-11-221-0/+66
| | | | | | | | | | | | | To do so, we must resolve all buffers on entering a glBegin/glEnd block. For the detailed explanation, see the Doxygen comments in this patch. v2: - Fix typo: s/enusure/ensure/. - In brwPrepareExecBegin(), do the same resolves as done by brw_predraw_resolve_buffers(). Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: remove #include of api_noop.hBrian Paul2011-11-111-1/+0
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* i965: Add new brw_context::max_gs_threads constant.Kenneth Graunke2011-10-251-0/+7
| | | | | | | | These are correct to the best of my knowledge, gleaned from a variety of internal sources. Sadly, the Sandybridge PRM has incorrect limits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename (vs|wm)_max_threads to max_(vs|wm)_threads for consistency.Kenneth Graunke2011-10-251-14/+14
| | | | | | | | | The inconsistency between vs_max_threads and max_vs_entries was rather annoying. I could never seem to remember which one was reversed, which made it harder to find quickly. "Max __ Threads" seems more natural. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove "single threaded" INTEL_DEBUG mode.Kenneth Graunke2011-10-251-5/+0
| | | | | | | | | | | | | | | | | According to the docs for 3DSTATE_PS (Gen7+) and 3DSTATE_WM (Gen6), there is a platform dependent value for the minimum number of pixel shader threads. It may also vary based on whether WIZ Hashing is on. For example, Ivybridge requires at least 4 threads if WIZ hashing is disabled, and 8 if it's enabled. Programming it to use less threads is illegal. Sandybridge appears to have similar restrictions. So on newer platforms, INTEL_DEBUG=sing will probably just hang the GPU. Rather than try to patch it up for newer platforms and extend it to support geometry shaders, just remove it as it isn't that useful anyway. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Set MaxIfDepth to UINT_MAX on Gen6+ and 16 on prior generations.Kenneth Graunke2011-10-211-0/+1
| | | | | | | | | | | | | Commit 488fe51cf823ccd137c667f1e92dd86f8323b723 converted the EmitNoIfs flag to MaxIfDepth, an unsigned integer saying "flatten if-statements nested beyond this depth." Unfortunately, i965 left this initialized to 0, which made ir_to_mesa attempt to flatten all if-statements. We didn't notice right away because we usually throw away ir_to_mesa's code in favor of the native VS and FS backends...but this still creates a lot of unnecessary work. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Initialize intel_context::vtbl after calling intelInitContext()Chad Versace2011-10-181-1/+2
| | | | | | | | | | | | intel_context::gen field is set by intelInitContext(). So, by calling intelInitContext() before initializing the vtable, we can can construct different vtables for different gens. Specifically, this allows us to set the HiZ operations to be no-ops for contexts for which HiZ is not enabled. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Convert from GLboolean to 'bool' from stdbool.h.Kenneth Graunke2011-10-181-22/+23
| | | | | | | | | | | | | | | | | I initially produced the patch using this bash command: for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i 's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i 's/GL_FALSE/false/g' $file; done Then I manually added #include <stdbool.h> to fix compilation errors, and converted a few functions back to GLboolean that were used in core Mesa's function pointer table to avoid "incompatible pointer" warnings. Finally, I cleaned up some whitespace issues introduced by the change. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Chad Versace <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Add support for GL_EXT_texture_array and GL_MESA_texture_array.Eric Anholt2011-10-031-0/+5
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* intel: Introduce a new intel_context::gt field to go along with gen.Kenneth Graunke2011-09-261-3/+3
| | | | | | | | | | It seems that GT1/GT2 sorts of variations are here to stay, and more special cases will likely be required in the future. Checking by PCI ID via the IS_xxx_GTx macros is cumbersome; introducing a new 'gt' field analogous to intel->gen will make this easier. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Enable lower_clip_distance.Paul Berry2011-09-231-0/+1
| | | | | | | | i965 requires gl_ClipDistance to be formatted as an array of 2 vec4's (as opposed to an array of 8 floats), so enable the lowering pass that performs this conversion. Reviewed-by: Eric Anholt <[email protected]>
* i965/vs: Switch to the new VS backend by default.Eric Anholt2011-09-081-1/+1
| | | | | | | | | | | Now instead of env INTEL_NEW_VS=1 to get it, you need INTEL_OLD_VS=1 to not get it. While it's not quite to the same codegen efficiency as the old backend, it is not regressing piglit on G965 and G45, and actually fixing bugs on gen6, and the remaining codegen quality regressions all appear tractable. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: add a UniformBooleanTrue optionBryan Cain2011-09-051-1/+3
| | | | | | | | Drivers supporting native integers set UniformBooleanTrue to the integer value that should be used for true when uploading uniform booleans. This is ~0 for Gallium and 1 for i965. Reviewed-by: Ian Romanick <[email protected]>
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