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path: root/src/mesa/drivers/dri/i965/brw_clip_util.c
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* i965: clip: Remove assumption about VUE header from brw_clip_interp_vertex()Paul Berry2011-09-061-5/+8
* i965: clip: Convert computations to ..._to_offset() for clarity.Paul Berry2011-09-061-10/+26
* i965: clip: Add a function to determine whether a vert_result is in use.Paul Berry2011-09-061-4/+4
* i965: clip: Rework brw_clip_interp_vertex() to use the VUE map.Paul Berry2011-09-061-5/+5
* i965: clip: Modify brw_clip_interp_vertex() to use the VUE map.Paul Berry2011-09-061-2/+2
* i965: clip: Move hpos_offest and ndc_offset into local functions.Paul Berry2011-09-061-2/+6
* i965: clip: rename header_position_offset to the more correct ndc_offset.Paul Berry2011-09-061-1/+1
* i965: Move IF stack handling into the EU abstraction layer/brw_compile.Kenneth Graunke2011-05-171-3/+2
* i965: Remove some duped register size/count definitionsEric Anholt2010-07-261-5/+0
* i965: Reduce repeated calculation of the attribute-offset-in-VUE.Eric Anholt2010-07-191-10/+3
* mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul2010-06-101-1/+1
* i965: remove disabled code for cycling through MRF registers in clipping.Eric Anholt2010-05-201-15/+2
* i965: Remove constant or ignored-by-hw args from FF sync message setup.Eric Anholt2010-05-181-12/+7
* intel: Clean up chipset name and gen num for IronlakeZhenyu Wang2010-04-211-2/+2
* Merge branch 'mesa_7_7_branch'Brian Paul2010-01-251-1/+0
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| * i965: Remove unnecessary headers.Vinson Lee2010-01-221-1/+0
* | intel: Replace IS_G4X() across the driver with context structure usage.Eric Anholt2009-12-221-3/+4
* | intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.Eric Anholt2009-12-221-2/+6
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* i965: Postpone ff_sync message in CLIP kernel on IGDNGXiang, Haihao2009-07-301-12/+36
* i965: add support for new chipsetsXiang, Haihao2009-07-131-0/+27
* mesa: added "main/" prefix to includes, remove some -I paths from Makefile.te...Brian Paul2008-09-181-4/+4
* 965: Fix incorrect backface cullingKrzysztof Czurylo2008-08-211-3/+2
* i965: valid message length includes message header.Xiang, Haihao2008-01-251-1/+1
* optimize 965 clipZou Nan hai2007-08-311-10/+2
* Add Intel i965G/Q DRI driver.Eric Anholt2006-08-091-0/+354
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