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* intel/compiler: Pass detailed dependency classes to invalidate_analysis()Francisco Jerez2020-03-0620-54/+61
| | | | | | | | | | | Have fun reading through the whole back-end optimizer to verify whether I've missed any dependency flags -- Or alternatively, just trust that any mistake here will trigger an assertion failure during analysis pass validation if it ever poses a problem for the consistency of any of the analysis passes managed by the framework. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
* intel/compiler: Define more detailed analysis dependency classesFrancisco Jerez2020-03-061-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I've deliberately separated this from the general analysis pass infrastructure in order to discuss it independently. The dependency classes defined here refer to state changes of several objects of the program IR, and are fully orthogonal and expected to change less often than the set of analysis passes present in the compiler back-end. The objective is to avoid unnecessary coupling between optimization and analysis passes in the back-end. By doing things in this way the set of flags to be passed to invalidate_analysis() can be determined from knowledge of a single optimization pass and a small set of well specified dependency classes alone -- IOW there is no need to audit all analysis passes to find out which ones might be affected by certain kind of program transformation performed by an optimization pass, as well as the converse, there is no need to audit all optimization passes when writing a new analysis pass to find out which ones can potentially invalidate the result of the analysis. The set of dependency classes defined here is rather conservative and mainly based on the requirements of the few analysis passes already part of the back-end. I've also used them without difficulty with a few additional analysis passes I've written but haven't yet sent for review. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
* intel/compiler: Introduce backend_shader method to propagate IR changes to ↵Francisco Jerez2020-03-0624-52/+93
| | | | | | | | | | | | | | | | | analysis passes The invalidate_analysis() method knows what analysis passes there are in the back-end and calls their invalidate() method to report changes in the IR. For the moment it just calls invalidate_live_intervals() (which will eventually be fully replaced by this function) if anything changed. This makes all optimization passes invalidate DEPENDENCY_EVERYTHING, which is clearly far from ideal -- The dependency classes passed to invalidate_analysis() will be refined in a future commit. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
* intel/compiler: Introduce simple IR analysis pass frameworkFrancisco Jerez2020-03-062-0/+147
| | | | | | | | | | | | Motivated in detail in the source code. The only piece missing here from the analysis pass infrastructure is some sort of mechanism to broadcast changes in the IR to all existing analysis passes, which will be addressed by a future commit. The analysis_dependency_class enum might seem a bit silly at this point, more interesting dependency categories will be defined later on. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
* intel/compiler: Reverse inclusion dependency between ↵Francisco Jerez2020-03-064-6/+3
| | | | | | | | | | | | | brw_vec4_live_variables.h and brw_vec4.h brw_vec4.h (in particular vec4_visitor) is logically a user of the live variables analysis pass, not the other way around. brw_vec4_live_variables.h requires the definition of some VEC4 IR data structures to compile, but those can be obtained directly from brw_ir_vec4.h without including brw_vec4.h. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
* intel/compiler: Reverse inclusion dependency between brw_fs_live_variables.h ↵Francisco Jerez2020-03-063-3/+4
| | | | | | | | | | | | | | | | and brw_fs.h brw_fs.h (in particular fs_visitor) is logically a user of the live variables analysis pass, not the other way around. brw_fs_live_variables.h requires the definition of some FS IR data structures to compile, but those can be obtained directly from brw_ir_fs.h without including brw_fs.h. The dependency of fs_live_variables on fs_visitor is rather accidental and will be removed in a future commit, a forward declaration is enough for the moment. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
* intel/compiler: Nest definition of live variables block_data structuresFrancisco Jerez2020-03-064-82/+83
| | | | | | | | | | | | | | | | When this commit was originally written, these two structures had the exact same name. Subsequently in commit 12a8f2616a2f (intel/compiler: Fix C++ one definition rule violations) they were renamed. Original commit message: > These two structures have exactly the same name which prevents the two > files from being included at the same time and could cause serious > trouble in the future if it ever leads to a (silent) violation of the > C++ one definition rule. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
* intel/compiler: Reverse inclusion dependency between brw_cfg.h and brw_shader.hFrancisco Jerez2020-03-064-6/+6
| | | | | | | | | This reflects the natural dependency relationship between brw_cfg.h and brw_shader.h. brw_cfg.h only requires the base IR definitions which are now part of a separate header. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
* intel/compiler: Move base IR definitions into a separate header fileFrancisco Jerez2020-03-063-157/+184
| | | | | | | | | | | | | | | | | | | | | This pulls out the i965 IR definitions into a separate file and leaves the top-level backend_shader structure and back-end compiler entry points in brw_shader.h. The purpose is to keep things tidy and prevent a nasty circular dependency between brw_cfg.h and brw_shader.h. The logical dependency between these data structures looks like: backend_shader (brw_shader.h) -> cfg_t (brw_cfg.h) -> bblock_t (brw_cfg.h) -> backend_instruction (brw_shader.h) This circular header dependency is currently resolved by using forward declarations of cfg_t/bblock_t in brw_shader.h and having brw_cfg.h include brw_shader.h, which seems backwards and won't work at all when the forward declarations of cfg_t/bblock_t are no longer sufficient in a future commit. Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4012>
* anv: Enable HiZ for VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMALJason Ekstrand2020-03-051-8/+19
| | | | | Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
* blorp: Write to depth/stencil images as depth/stencil when possibleJason Ekstrand2020-03-053-18/+77
| | | | | | | | | | | | | | | On Gen4 and G45 and earlier, we have to handle weird offsetting to write to depth and stencil due to a lack of proper depth mipmapping support in hardware. On Gen6, we have to deal with strange HiZ and stencil layouts. Prior to Gen9, we also had to do crazy things for stencil writes because we didn't support GL_ARB_shader_stencil_export and friends in hardware. However, starting with Gen7 for depth and Gen9 for stencil, we can easily write out with the "right" hardware. This allows us to leave HiZ and other compression enabled for blorp_blit() and blorp_copy() operations. Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
* isl: Set 3DSTATE_DEPTH_BUFFER::Depth correctly for 3D surfacesJason Ekstrand2020-03-051-1/+19
| | | | | | Cc: [email protected] Reviewed-by: Nanley Chery <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3717>
* intel/gen12+: Disable mid thread preemption.Rafael Antognolli2020-03-032-0/+13
| | | | | | | | | | | | | Fixes a GPU hang in Car Chase. Cc: [email protected] v2: Add comment explaining why (Jason). Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035>
* intel/isl: Implement D16_UNORM workarounds.Rafael Antognolli2020-03-034-2/+75
| | | | | | | | | | | | | | | | | | | | | | | | GEN:BUG:14010455700 (lineage 1808121037): "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501. GEN:BUG:1806527549: "Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM." This one could fix a GPU hang in some workloads. v2: Implement WA in isl and add another similar WA (Jason). v3: Add flushes before changing chicken registers (Jason) v4: Depth flush and stall + end of pipe sync when changing registers (Jason). Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
* anv: multiply the scratch space by 4 on gen9-10 like iris and i965Paulo Zanoni2020-03-031-2/+16
| | | | | | | | | | | | | | | | | | | My understanding is that there's no reason for the scratch space allocation to be different between iris, i965 and anv. Let's make all the functions behave the same. I don't know if this fixes any specific gen9 bugs, it it might since it increases the scratch space. v2: Rebase. v3: Rebase. v4: Remove redundant gen 11 check (Jason). Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
* intel/device: bdw_gt1 actually has 6 eus per subslicePaulo Zanoni2020-03-031-1/+1
| | | | | | | | | | | | | | | | | | | Found by inspection, I'm not aware of any bugs caused by this typo. According to Lionel, it seems we only use this to generate masks of available EUs for perfromance queries, and it's only used when we can't query the fused parts of the GPU through DRM_IOCTL_I915_QUERY. So this patch should help for the corner case where the Kernel is too old to support the query ioctl. v2: improve commit message, cc stable (Lionel). Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
* intel: fix the gen 12 compute shader scratch IDsPaulo Zanoni2020-03-031-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | This is the same idea as "intel: fix the gen 11 compute shader scratch IDs". The number of EUs on TGL is not the same as ICL, but the MEDIA_VFE_STATE restrictions stay the same, so adapt the code to it. Also, consider the base configuration instead of what we read from the Kernel. According to Mark, this fixes the following piglit tests on TGL: piglit.spec.arb_compute_shader.execution.shared-atomicmax-uint.tglm64 piglit.spec.arb_compute_shader.execution.shared-atomicmax-int.tglm64 piglit.spec.intel_shader_atomic_float_minmax.execution.shared-atomicmax-float.tglm64 v2: s/ICL+/Gen11+/ (Jason). Cc: [email protected] Tested-by: Mark Janes <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
* intel: fix the gen 11 compute shader scratch IDsPaulo Zanoni2020-03-031-1/+6
| | | | | | | | | | | | | | | | | | | Scratch space allocation is based on the number of threads in the base configuration, and we only have one base configuration for ICL, with 8 subslices. This fixes an issue with Aztec on Vulkan in a machine with a configuration that's not the base. The issue looks like a regression from b9e93db20896, but it seems things are broken since forever, just not easily reproducible. v2: Reimplement it using the subslices variable. Don't touch TGL. Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4006>
* anv: Wait for the GPU to be idle before invalidating the aux table.Rafael Antognolli2020-03-021-0/+10
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
* anv: Do end-of-pipe sync around MCS/CCS ops instead of CS stallJason Ekstrand2020-03-022-8/+8
| | | | | | | | v2: Do end-of-pipe sync after clear depth stencil too (Jason). v3: Also do end-of-pipe sync before clear depth stencil too (Jason). Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
* anv: Use a proper end-of-pipe sync instead of just CS stallJason Ekstrand2020-03-022-15/+118
| | | | | Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
* anv: Use the PIPE_CONTROL instead of bits for the CS stall W/AJason Ekstrand2020-03-021-3/+7
| | | | | Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4005>
* intel/tools/dump_gpu: fix getparam valuesLionel Landwerlin2020-03-021-1/+8
| | | | | | | | | Don't return the pci_id for all params Fixes: 76bf38eaf0b6 ("intel/tools/aub_dump: move aub file initialization to maybe_init()") Reviewed-by: Tapani Pälli <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3994> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3994>
* intel/compiler: Restrict cs_threads to 64Jordan Justen2020-02-281-1/+3
| | | | | | | | | | | | | | | | | | | Our current GPGPU_WALKER code only supports up to 64 threads. On HSW we could use up to 70 and TGL up to 112, but only if the walker is adjusted so the width does not exceed 64. Work to support this is in progress. Previous to this change, we might try to downgrade to SIMD8 if the SIMD16 shader spilled. Since HSW and TGL have the max number of threads above 64, we would then try to emit an invalid GPGPU walker command. Fixes: 932045061b5 ("i965/cs: Emit compute shader code and upload programs") Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Tested-by: Paulo Zanoni <[email protected]>
* anv: Remove unused field `urb.total_size`Caio Marcelo de Oliveira Filho2020-02-274-10/+5
| | | | | | | | | | This was used before the URB calculation functions were shared by GL and Vulkan. Also drop the substruct for the remaining, `l3_config` is a good name on its own. Also-written-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3981> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3981>
* anv: Remove unused field xfb_used from anv_pipelineCaio Marcelo de Oliveira Filho2020-02-272-5/+1
| | | | | | | | | | Since we only use xfb_info for GEN >= 8, make the ifdef cover that local variable. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3973> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3973>
* nir: Drop nir_tex_instr::texture_array_sizeJason Ekstrand2020-02-262-6/+0
| | | | | | | | | | It's set by lots of things and we spend a lot of time maintaining it but no one actually uses the value for anything useful. Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3940> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3940>
* intel/tools: Do not print type/qualifiers/name for c_literalMatt Turner2020-02-251-1/+1
| | | | | | | | External tools may wish to choose their own type, qualifiers, and name, so do not emit our own. Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
* intel/tools: Allow i965_disasm to disassemble c_literal input typeSagar Ghuge2020-02-251-36/+103
| | | | | | | | | | | | | | | | Added extra argument named 'type' which can be 'bin' (default if ommited) or 'c_literal' for input type. Change 'binary-path' argument name to 'input-path'. v2: - Use util_dynarray for assembly (Matt Turner) - Read data in 8 bytes chunk (Matt Turner) - Fix help option (Akeem Abodunrin) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
* intel/tools: Print c_literals 4 byte wideSagar Ghuge2020-02-251-4/+12
| | | | | | | | | | | | We already print hex value a byte wide, instead of printing c_literal byte wide, we can print it 4 byte wide, which gives us 2 different combinations. v2: Fix the aliasing issue (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
* intel/tools: Add test for state register as sourceSagar Ghuge2020-02-252-0/+2
| | | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
* intel/tools: Add test for address register as sourceSagar Ghuge2020-02-252-0/+2
| | | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
* intel/tools: Set correct address register file and number in i965_asmSagar Ghuge2020-02-251-1/+3
| | | | | | | | | We need to use already created brw_reg and set correct file type, register number and sub register number. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
* intel/tools: Handle STATE_REG in typed source operandSagar Ghuge2020-02-251-2/+4
| | | | | | | | | | Also stop using brw_sr0_reg function as it return new brw_reg, we already created register, all we have to is just set file, register number and subnr. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
* intel/tools: Handle illegal instructionSagar Ghuge2020-02-251-0/+10
| | | | | | | | | Allow assembler to handle illegal instruction even though mesa doesn't use it but might be required at some point in future. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3952>
* anv: Always enable the data cacheJason Ekstrand2020-02-253-10/+1
| | | | | | | | | | | | | | | | | Because we set the needs_data_cache bit from the NIR during compilation, any time a shader was pulled out of the pipeline cache, we wouldn't set the bit and the data cache was disabled. Fortunately, on Gen8+, this bit is ignored because we always use the ALL section in the L3$ config instead of separate DC and RO sections. On Gen7, however, this meant that we were basically never running with the data cache enabled and our compute performance was suffering massively because of it. This commit improves Geekbench 5 scores on my Haswell GT3 by roughly 330% (no, that's not a typo). Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3912>
* intel/aub_dump: stub the waits when overriding the deviceLionel Landwerlin2020-02-251-0/+19
| | | | | | | | | | We don't actually want to wait on anything, just complete submitting the commands as fast as possible. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
* intel/tools/aub_dump: fix crash when using the default legacy contextLionel Landwerlin2020-02-251-4/+5
| | | | | | | | | When execbuffer->rsvd1 == 0, the legacy context is used. Ensure we have context created for this. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
* intel/tools/aub_dump: move aub file initialization to maybe_init()Lionel Landwerlin2020-02-251-38/+33
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3705>
* intel/isl: Add isl_aux_info.c to Makefile.sourcesJason Ekstrand2020-02-251-0/+1
| | | | | | | | | | This should fix the Android build. Fixes: 58d4749e56 "isl: Add a module which manages aux resolves" Reviewed-by: Nanley Chery <[email protected]> Reported-by: Clayton Craft <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3934> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3934>
* intel/blorp: Implement GEN:BUG:1605967699.Rafael Antognolli2020-02-251-8/+44
| | | | | | | | | | v2: - Update comments and refactor code (Lionel). - Only apply workaround to stencil resolves. Acked-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3909> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3909>
* nir, intel: Move use_scoped_memory_barrier to nir_optionsCaio Marcelo de Oliveira Filho2020-02-242-2/+2
| | | | | | | | | | | This option will be used later by GLSL, so move to a common struct. Because nir_options is filled in the compiler instead of the Vulkan driver, fix that up. GLSL will ignore that for now. Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3913>
* nir: Move intel's intrinsic_image_coordinate_components() to core nir.Eric Anholt2020-02-241-22/+1
| | | | | | | | This is a query that both Intel and freedreno need to do. We can simplify it a lot with the new glsl_get_sampler_dim_coordinate_components() Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3728>
* isl: Add a module which manages aux resolvesNanley Chery2020-02-244-0/+702
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a generic interface which manages aux resolves in ISL. The feature differences between this and what's in iris is: * Support for media compression. ISL_AUX_USAGE_MC behaves differently from many other usages of CCS, so it was useful to implement this support upfront, while designing the interfaces. * Optimizations for full-surface writes. For example, after a full-surface write occurs with ISL_AUX_USAGE_CCS_E in the PARTIAL_CLEAR state, isl_aux_state_transition_write() returns COMPRESSED_NO_CLEAR instead of COMPRESSED_CLEAR. A performance suggestion for main-surface-invalidating/replacing writes is given as a comment instead of adding a boolean to isl_aux_prepare_access(). This avoids extra validation and should be simple enough for the caller to handle. v2. Add assertions. (Jason) v3. Use switches in 2 more functions. (Jason) Store aux metadata in a static table. (Jason) Change prepare and finish function signatures. (Jason) Keep isl_aux_state_transition_* functions separate. v4. (Jason) Assert against resolving in AUX_INVALID. Rename aux_info struct to aux_usage_info. Drop the justification for each aux_usage_info field. Split out the NONE case in write function. Restructure tests to more easily confirm coverage. Rename access_compressed field to compressed. Make write behavior less ambiguous. v5. (Jason) Add more detail above WRITES_RESOLVE_AMBIGUATE. Add ISL_AUX_USAGE_MC to WritesResolveAmbiguate. Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
* anv: Add pipe_state_for_stage() helperCaio Marcelo de Oliveira Filho2020-02-211-13/+24
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3911> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3911>
* anv: Use intel_debug_flag_for_shader_stage()Caio Marcelo de Oliveira Filho2020-02-211-10/+1
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3911>
* intel/fs: Correctly handle multiply of fsign with a source modifierIan Romanick2020-02-191-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The other source of the multiply will be interpreted as a uint32_t in an XOR instruction. Any source modifiers with either not be interpreted at all or will be misinterpreted due to the differing types. If the other operand of the multiplication has a source modifier, just emit an extra move to resolve the source modifiers. The negation source modifier problem is difficult to reproduce due to an algebraic optimization that changes (-a*b) to -(a*b). However, changes in MR !1359 push the negations back down. On Gen7+ it might be possible to do slightly better for an abs() source modifier by using BFI2 as a glorified copysign(). On Gen8+ it might be possible to do slightly better for a neg() source modifier by emitting (~a ^ b). There were no shader-db changes on any Intel platform, so I think we can deal with that problem when it arises. See also piglit!224. Fixes: 06d2c116415 ("intel/fs: Add a scale factor to emit_fsign") Reviewed-by: Matt Turner <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3780> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3780>
* anv: Drop anv_image.c:get_surface()Chad Versace2020-02-191-10/+6
| | | | | | | | | It was called exactly once, and even there it returned the wrong surface in a corner case. Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3882> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3882>
* intel/compiler: Do not qsort zero sized arrayDanylo Piliaiev2020-02-191-2/+4
| | | | | | | | | | | | | | | | | | | | | ../src/intel/compiler/brw_nir_analyze_ubo_ranges.c:316:4: runtime error: null pointer passed as argument 1, which is declared to never be null #0 0x7f78f5916611 in brw_nir_analyze_ubo_ranges ../src/intel/compiler/brw_nir_analyze_ubo_ranges.c:316 #1 0x7f78f255c189 in brw_codegen_wm_prog ../src/mesa/drivers/dri/i965/brw_wm.c:97 #2 0x7f78f2565571 in brw_fs_precompile ../src/mesa/drivers/dri/i965/brw_wm.c:608 #3 0x7f78f24edd2c in brw_shader_precompile ../src/mesa/drivers/dri/i965/brw_link.cpp:56 #4 0x7f78f24f3af8 in brw_link_shader ../src/mesa/drivers/dri/i965/brw_link.cpp:381 #5 0x7f78f39a302a in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3119 #6 0x7f78f3a43826 in create_new_program ../src/mesa/main/ff_fragment_shader.cpp:1133 #7 0x7f78f3a43d00 in _mesa_get_fixed_func_fragment_program ../src/mesa/main/ff_fragment_shader.cpp:1163 #8 0x7f78f325ddcd in update_program ../src/mesa/main/state.c:134 #9 0x7f78f325fe64 in _mesa_update_state_locked ../src/mesa/main/state.c:360 #10 0x7f78f32600f1 in _mesa_update_state ../src/mesa/main/state.c:394 #11 0x7f78f2b3e587 in clear ../src/mesa/main/clear.c:169 #12 0x7f78f2b3e587 in _mesa_Clear ../src/mesa/main/clear.c:242 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
* brw_fs: Avoid zero size vlaDanylo Piliaiev2020-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | ../src/intel/compiler/brw_fs.cpp:2247:46: runtime error: variable length array bound evaluates to non-positive value 0 #0 0x7f78f5697678 in fs_visitor::assign_constant_locations() ../src/intel/compiler/brw_fs.cpp:2247 #1 0x7f78f571d29e in fs_visitor::optimize() ../src/intel/compiler/brw_fs.cpp:7361 #2 0x7f78f574eb84 in fs_visitor::run_fs(bool, bool) ../src/intel/compiler/brw_fs.cpp:8022 #3 0x7f78f575641b in brw_compile_fs ../src/intel/compiler/brw_fs.cpp:8408 #4 0x7f78f255c8e4 in brw_codegen_wm_prog ../src/mesa/drivers/dri/i965/brw_wm.c:123 #5 0x7f78f2565571 in brw_fs_precompile ../src/mesa/drivers/dri/i965/brw_wm.c:608 #6 0x7f78f24edd2c in brw_shader_precompile ../src/mesa/drivers/dri/i965/brw_link.cpp:56 #7 0x7f78f24f3af8 in brw_link_shader ../src/mesa/drivers/dri/i965/brw_link.cpp:381 #8 0x7f78f39a302a in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3119 #9 0x7f78f3a43826 in create_new_program ../src/mesa/main/ff_fragment_shader.cpp:1133 #10 0x7f78f3a43d00 in _mesa_get_fixed_func_fragment_program ../src/mesa/main/ff_fragment_shader.cpp:1163 #11 0x7f78f325ddcd in update_program ../src/mesa/main/state.c:134 #12 0x7f78f325fe64 in _mesa_update_state_locked ../src/mesa/main/state.c:360 #13 0x7f78f32600f1 in _mesa_update_state ../src/mesa/main/state.c:394 #14 0x7f78f2b3e587 in clear ../src/mesa/main/clear.c:169 #15 0x7f78f2b3e587 in _mesa_Clear ../src/mesa/main/clear.c:242 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3825>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-12 02:10:38 +0000