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* intel/genxml: replace gen_sort_tags.py MIT licence with SPDX equivalentEric Engestrom2020-06-131-20/+1
| | | | | | | | Much more readable with the same information :) Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5362>
* intel/genxml: drop python 2 support for gen_sort_tags.pyEric Engestrom2020-06-131-4/+1
| | | | | | | | | Python 2 is dead and this script is only run by devs, all of which have had python3 available for basically forever. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5362>
* intel/genxml: Migrate from deprecated xml.etree.ElementTree getchildren.Vinson Lee2020-06-061-6/+6
| | | | | | | | | xml.etree.ElementTree getchildren was deprecated since Python 2.7 and will be removed in Python 3.9. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5348>
* Switch from cElementTree to ElementTree.Vinson Lee2020-06-052-2/+2
| | | | | | | | | | | | | | The xml.etree.cElementTree module will be removed in Python 3.9. Since Python 3.3 the xml.etree.cElementTree module has been deprecated, the xml.etree.ElementTree module uses a fast implementation whenever available. Builds using Python 2.7 can still work but with the slower implementation. Signed-off-by: Vinson Lee <[email protected]> Acked-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5349>
* intel: fix gen_sort_tags.pyEric Engestrom2020-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | | The script was failing for me (python 3.8), not sure if this is a recent python version break or not as I don't know how often people have been running this script: Processing ./gen9.xml... Traceback (most recent call last): File "./gen_sort_tags.py", line 177, in <module> main() File "./gen_sort_tags.py", line 170, in main genxml[:] = enums + sorted_structs.values() + instructions + registers TypeError: can only concatenate list (not "odict_values") to list Turning the odict into a list fixes it for me, and the resulting xml file are identical to before :) Fixes: 903e142f0d35bc550ffd ("genxml: add a sorting script") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5352>
* intel/genxml: drop sort_xml.sh and move the loop directly in gen_sort_tags.pyEric Engestrom2020-06-053-19/+12
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5353>
* intel/genxml: add PIPE_CONTROL command cache invalidate bitLionel Landwerlin2020-05-202-0/+2
| | | | | | | | | This new bit invalidates the cache/prefetch of commands in the command streamer. This will be useful for self modifying batches. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* intel/genxml: fix bits generation for MI_LOAD_REGISTER_IMMLionel Landwerlin2020-05-201-8/+12
| | | | | | | | | | | | | | | | | | | | | This instruction has a group with the same name than another field above : <field name="Data DWord" start="64" end="95" type="uint"/> <group count="0" start="96" size="64"> <field name="Register Offset" start="2" end="22" type="offset"/> <field name="Data DWord" start="32" end="63" type="uint"/> </group> The script was replacing the offset of the field first with the second one in the group. This change ignore anything a group within an instruction. v2: Drop unused variable (Rafael) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>
* genxml: pack: deal with default field not being simple integersLionel Landwerlin2020-05-091-1/+7
| | | | | | | | | Storing integers into enums doesn't seem to cause issues in C, but with our builder tests written in C++ this causes warnings/errors. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>
* genxml: factor out utility functionsLionel Landwerlin2020-05-093-46/+40
| | | | | | | | | v2: Use the regexp version (Jordan) Also fix regexp that missed the ' character replacement (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>
* genxml: fix invalid end value for video fieldsLionel Landwerlin2020-05-094-4/+4
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>
* genxml: run sorting scriptLionel Landwerlin2020-05-092-25/+25
| | | | | | | | Helps running diff/meld between generations :) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4938>
* anv,iris: Fix input vertex max for tcs on gen12D Scott Phillips2020-05-011-1/+1
| | | | | | | | | | | | | gen12 does away with the single patch dispatch mode for tcs, and increases some limits so that 8_patch mode can always work. Make the necessary changes so we don't try to fall back to single patch mode. Fixes KHR-GL46.tessellation_shader.single.max_patch_vertices and others Fixes: 44754279ace7 ("intel/fs/gen12: Use TCS 8_PATCH mode.") Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4843>
* intel/gen12: Add XML description for 3DSTATE_PRIMITIVE_REPLICATIONCaio Marcelo de Oliveira Filho2020-04-071-0/+16
| | | | | | | | | v2: Use groups for the 16-element arrays "Viewport Offset" and "RTAI Offset". (Ken) Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2313>
* intel/genxml: Add patch count threshold field on gen12Sagar Ghuge2020-03-231-0/+1
| | | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3563>
* intel/gen12+: Disable mid thread preemption.Rafael Antognolli2020-03-031-0/+1
| | | | | | | | | | | | | Fixes a GPU hang in Car Chase. Cc: [email protected] v2: Add comment explaining why (Jason). Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4035>
* intel/isl: Implement D16_UNORM workarounds.Rafael Antognolli2020-03-031-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | GEN:BUG:14010455700 (lineage 1808121037): "To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface Format is D16_UNORM , surface type is not NULL & 1X_MSAA" Required for fixing ttps://gitlab.freedesktop.org/mesa/mesa/issues/2501. GEN:BUG:1806527549: "Set HIZ_CHICKEN (7018h) bit 13 = 1 when depth buffer is D16_UNORM." This one could fix a GPU hang in some workloads. v2: Implement WA in isl and add another similar WA (Jason). v3: Add flushes before changing chicken registers (Jason) v4: Depth flush and stall + end of pipe sync when changing registers (Jason). Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3801>
* intel/genxml: Drop "reserved" enumKenneth Graunke2020-02-051-1/+0
| | | | | | | | | | | This was adding "#define reserved 2" to genxml includes, which is a fairly mean lowercase word to redefine. It ends up breaking the build on Android, which has __u32 reserved fields in headers. Defining it also has no purpose. Just drop it. Fixes: 5bea0cf7795 ("intel/isl: Move iris's pipe-to-isl format function to isl.") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3729>
* intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11Jason Ekstrand2020-01-301-1/+0
| | | | | | | | | | | | SML is no longer in the L3$ on Gen11+. It's not incredibly clear from the docs but no Gen11 platforms are in the list of platforms on which this bit exists. Also, we've been always setting it false on Gen11 in ANV and i965 thanks to GEN_L3P_SLM being zero with no ill effects. Cc: "20.0" [email protected] Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* genxml: Add a new 3DSTATE_SF field on gen12Jason Ekstrand2020-01-301-0/+5
| | | | | | | Cc: [email protected] Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
* intel/genxml: Make SO_DECL::"Hole Flag" a BooleanJason Ekstrand2020-01-277-7/+7
| | | | | Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
* genxml: add new Gen11+ PIPE_CONTROL fieldLionel Landwerlin2020-01-162-0/+2
| | | | | | | | | PIPE_CONTROL gained a new field in its first DWORD on Gen11. We had no use for it so far, but we start using it on Gen12. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3408>
* genxml: Remove a non-existant HW bitJason Ekstrand2020-01-093-3/+0
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* intel/genxml: Add a partial TCCNTLREG definitionKenneth Graunke2019-12-101-0/+7
| | | | | | | TCCNTLREG contains additional cache programming settings. In particular, there are several write combining controls we'd like to use. Acked-by: Jason Ekstrand <[email protected]>
* intel/genxml: Add 3DSTATE_CONSTANT_ALL packet.Rafael Antognolli2019-12-041-0/+25
| | | | Acked-by: Caio Marcelo de Oliveira Filho <[email protected]>
* genxml: Mark everything in genX_pack.h always_inlineJason Ekstrand2019-11-181-8/+8
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add gen12 tile cache flush bitJordan Justen2019-10-301-0/+1
| | | | Signed-off-by: Jordan Justen <[email protected]>
* genxml/gen12: Add Stencil Buffer Resolve Enable bitSagar Ghuge2019-10-291-0/+1
| | | | | Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* genxml: Add 3DSTATE_SO_BUFFER_INDEX_* instructionsPlamena Manolova2019-10-291-0/+47
| | | | | | | | For gen12 we set the streamout buffers using 4 separate commands instead of 3DSTATE_SO_BUFFER. Signed-off-by: Plamena Manolova <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* genxml: Change 3DSTATE_DEPTH_BOUNDS bias.Plamena Manolova2019-10-291-1/+1
| | | | | | | | | The bias for the 3DSTATE_DEPTH_BOUNDS instruction should be 2 not 1. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel: Fix and use HIZ_CCS write through modeNanley Chery2019-10-281-0/+1
| | | | | | | | Write through to the CCS if the surface is used as a texture and can be sampled by the HW with CCS. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnableNanley Chery2019-10-281-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Use RENDER_SURFACE_STATE::DepthStencilResourceNanley Chery2019-10-281-0/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/blorp/gen12: Set FWCC when storing the clear color.Rafael Antognolli2019-10-281-0/+1
| | | | | | | | | | | | | | | | | | | | From "Render Target Fast Clear" description for Gen12: "SW must store clear color using MI_STORE_DATA_IMM with ForceWriteCompletionCheck bit set." From Instruction_MI_STORE_DATA_IMM, bitfield 10 (when set to 1): "Following the last write from this command, Command Streamer will wait for all previous writes are completed and in global observable domain before moving to next command." We use 4 SDIs to store the clear color (one per channel). From the description, it looks to me that setting that flag only on the last SDI should be enough. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* genxml: Add 3DSTATE_DEPTH_BOUNDS instruction.Plamena Manolova2019-10-281-0/+13
| | | | | | | | In gen12 we add the 3DSTATE_DEPTH_BOUNDS instruction which enables support for depth bounds testing. Signed-off-by: Plamena Manolova <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml/gen12: Add AUX MAP register definitionsJordan Justen2019-10-281-0/+8
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-238-0/+40
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-234-0/+72
| | | | | | | | | | We have 2 of those we can configure to source programmable events. Those are not part of the OA reports. Configuration happens in i915 through the metric set selected by the application. On the Mesa side we'll just sample those and do a diff. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* intel/genxml: Remove W-tiling on gen12Jason Ekstrand2019-10-171-1/+0
| | | | | | It's no longer supported by the hardware Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml,isl: Add gen12 stencil buffer changesJordan Justen2019-10-171-5/+30
| | | | | | | | | Rework: * NULL stencil buffer path (Jason) * genxml fixes (Nanley) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml,isl: Add gen12 depth buffer changesJordan Justen2019-10-171-9/+13
| | | | | | | | | Reworks: * Fix 3DSTATE_DEPTH_BUFFER "Surface Format" end in xml (Jason) * Remove WM_HZ_OP changes (Nanley) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml,isl: Add gen12 render surface state changesJordan Justen2019-10-171-10/+9
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/genxml: Stop manually scrubbing 'α' -> "alpha"Kenneth Graunke2019-09-232-2/+1
| | | | | | | 'α' has never appeared in any genxml files, so there's no need to replace it with the word "alpha". Reviewed-by: Jordan Justen <[email protected]>
* genxml/gen11+: Add COMMON_SLICE_CHICKEN4 registerAnuj Phogat2019-09-112-0/+10
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv,iris: L3ALLOC register replaces L3CNTLREG for gen12Jordan Justen2019-09-061-4/+3
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/genxml: Build gen12 genxmlJordan Justen2019-08-284-0/+7
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Add gen12.xml as a copy of gen11.xmlJordan Justen2019-08-281-0/+7171
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Run sort_xml.sh to tidy gen9.xml and gen11.xmlJordan Justen2019-08-282-38/+36
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml/gen11: Add spaces in EnableUnormPathInColorPipeJordan Justen2019-08-281-1/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Handle field names with different spacing/hyphenJordan Justen2019-08-281-3/+4
| | | | | | | | | | | | | If a field name differs slightly between two generations then this change will still add the fields into the same group. For example, these will be treated as equal: * "Software Exception" and "Software Exception" * "Per Thread" and "Per-Thread" Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
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