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* intel/genxml: add PIPE_CONTROL command cache invalidate bitLionel Landwerlin2020-05-202-0/+2
* intel/genxml: fix bits generation for MI_LOAD_REGISTER_IMMLionel Landwerlin2020-05-201-8/+12
* genxml: pack: deal with default field not being simple integersLionel Landwerlin2020-05-091-1/+7
* genxml: factor out utility functionsLionel Landwerlin2020-05-093-46/+40
* genxml: fix invalid end value for video fieldsLionel Landwerlin2020-05-094-4/+4
* genxml: run sorting scriptLionel Landwerlin2020-05-092-25/+25
* anv,iris: Fix input vertex max for tcs on gen12D Scott Phillips2020-05-011-1/+1
* intel/gen12: Add XML description for 3DSTATE_PRIMITIVE_REPLICATIONCaio Marcelo de Oliveira Filho2020-04-071-0/+16
* intel/genxml: Add patch count threshold field on gen12Sagar Ghuge2020-03-231-0/+1
* intel/gen12+: Disable mid thread preemption.Rafael Antognolli2020-03-031-0/+1
* intel/isl: Implement D16_UNORM workarounds.Rafael Antognolli2020-03-031-0/+10
* intel/genxml: Drop "reserved" enumKenneth Graunke2020-02-051-1/+0
* intel/genxml: Drop SLMEnable from L3CNTLREG on Gen11Jason Ekstrand2020-01-301-1/+0
* genxml: Add a new 3DSTATE_SF field on gen12Jason Ekstrand2020-01-301-0/+5
* intel/genxml: Make SO_DECL::"Hole Flag" a BooleanJason Ekstrand2020-01-277-7/+7
* genxml: add new Gen11+ PIPE_CONTROL fieldLionel Landwerlin2020-01-162-0/+2
* genxml: Remove a non-existant HW bitJason Ekstrand2020-01-093-3/+0
* intel/genxml: Add a partial TCCNTLREG definitionKenneth Graunke2019-12-101-0/+7
* intel/genxml: Add 3DSTATE_CONSTANT_ALL packet.Rafael Antognolli2019-12-041-0/+25
* genxml: Mark everything in genX_pack.h always_inlineJason Ekstrand2019-11-181-8/+8
* intel/genxml: Add gen12 tile cache flush bitJordan Justen2019-10-301-0/+1
* genxml/gen12: Add Stencil Buffer Resolve Enable bitSagar Ghuge2019-10-291-0/+1
* genxml: Add 3DSTATE_SO_BUFFER_INDEX_* instructionsPlamena Manolova2019-10-291-0/+47
* genxml: Change 3DSTATE_DEPTH_BOUNDS bias.Plamena Manolova2019-10-291-1/+1
* intel: Fix and use HIZ_CCS write through modeNanley Chery2019-10-281-0/+1
* intel: Use 3DSTATE_DEPTH_BUFFER::ControlSurfaceEnableNanley Chery2019-10-281-0/+1
* intel: Use RENDER_SURFACE_STATE::DepthStencilResourceNanley Chery2019-10-281-0/+1
* intel/blorp/gen12: Set FWCC when storing the clear color.Rafael Antognolli2019-10-281-0/+1
* genxml: Add 3DSTATE_DEPTH_BOUNDS instruction.Plamena Manolova2019-10-281-0/+13
* genxml/gen12: Add AUX MAP register definitionsJordan Justen2019-10-281-0/+8
* intel/genxml: add RPSTAT register for core frequencyLionel Landwerlin2019-10-238-0/+40
* intel/genxml: add generic perf counters registersLionel Landwerlin2019-10-234-0/+72
* intel/genxml: Remove W-tiling on gen12Jason Ekstrand2019-10-171-1/+0
* intel/genxml,isl: Add gen12 stencil buffer changesJordan Justen2019-10-171-5/+30
* intel/genxml,isl: Add gen12 depth buffer changesJordan Justen2019-10-171-9/+13
* intel/genxml,isl: Add gen12 render surface state changesJordan Justen2019-10-171-10/+9
* intel/genxml: Stop manually scrubbing 'α' -> "alpha"Kenneth Graunke2019-09-232-2/+1
* genxml/gen11+: Add COMMON_SLICE_CHICKEN4 registerAnuj Phogat2019-09-112-0/+10
* anv,iris: L3ALLOC register replaces L3CNTLREG for gen12Jordan Justen2019-09-061-4/+3
* intel/genxml: Build gen12 genxmlJordan Justen2019-08-284-0/+7
* intel/genxml: Add gen12.xml as a copy of gen11.xmlJordan Justen2019-08-281-0/+7171
* intel/genxml: Run sort_xml.sh to tidy gen9.xml and gen11.xmlJordan Justen2019-08-282-38/+36
* intel/genxml/gen11: Add spaces in EnableUnormPathInColorPipeJordan Justen2019-08-281-1/+1
* intel/genxml: Handle field names with different spacing/hyphenJordan Justen2019-08-281-3/+4
* isl: Enable Unorm Path in Color PipeKenneth Graunke2019-08-151-0/+1
* intel/genxml: Update 3D_MODE and add SLICE_HASH_TABLE.Rafael Antognolli2019-08-121-1/+33
* intel/genxml: Add GT_MODE hashing defs for Gen9.Francisco Jerez2019-08-121-0/+17
* genxml: Rename 3DSTATE_SF::Anti-Aliasing EnableJason Ekstrand2019-08-066-6/+6
* intel/genxml: Add basic infra for encoding/decoding unit tests.Rafael Antognolli2019-07-231-0/+2
* intel/genxml: correct bit fields in CACHE_MODE_0 reg for gen11Dongwon Kim2019-07-081-16/+14
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