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* intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 modeJason Ekstrand2019-02-041-7/+6
* intel/fs: Use split sends for surface writes on gen9+Jason Ekstrand2019-01-292-18/+47
* intel/fs: Add interference between SENDS sourcesJason Ekstrand2019-01-291-0/+27
* intel/fs: Support SENDS in SHADER_OPCODE_SENDJason Ekstrand2019-01-293-8/+66
* intel/disasm: Properly disassemble split sendsJason Ekstrand2019-01-291-19/+142
* intel/eu: Add support for the SENDS[C] messagesJason Ekstrand2019-01-294-19/+255
* intel/inst: Indent some codeJason Ekstrand2019-01-291-177/+183
* intel/inst: Fix the ia16_addr_imm helpersJason Ekstrand2019-01-291-4/+5
* intel/disasm: Rework SEND decoding to use descriptorsJason Ekstrand2019-01-291-36/+50
* intel/eu: Add more message descriptor helpersJason Ekstrand2019-01-291-27/+216
* intel/eu/validate: SEND restrictions also apply to SENDCJason Ekstrand2019-01-291-1/+2
* intel/eu: Use GET_BITS in brw_inst_set_send_ex_descJason Ekstrand2019-01-291-5/+5
* intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+Jason Ekstrand2019-01-297-88/+25
* intel/fs: Use SHADER_OPCODE_SEND for texturing on gen7+Jason Ekstrand2019-01-294-142/+177
* intel/fs: Use a logical opcode for IMAGE_SIZEJason Ekstrand2019-01-294-6/+21
* intel/fs: Use SHADER_OPCODE_SEND for surface messagesJason Ekstrand2019-01-295-214/+201
* intel/fs: Add a generic SEND opcodeJason Ekstrand2019-01-299-3/+91
* intel/eu: Rework surface descriptor helpersJason Ekstrand2019-01-292-234/+234
* intel/eu: Add has_simd4x2 bools to surface_write functionsJason Ekstrand2019-01-291-6/+8
* intel/fs: Take an explicit exec size in brw_surface_payload_size()Jason Ekstrand2019-01-291-20/+39
* intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()Jason Ekstrand2019-01-291-0/+2
* intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITSJason Ekstrand2019-01-291-2/+2
* intel/fs: Get rid of fs_inst::equalsJason Ekstrand2019-01-292-23/+7
* intel/compiler: Add a file-level description of brw_eu_validate.cMatt Turner2019-01-261-1/+13
* intel/compiler: Reset default flag register in brw_find_live_channel()Matt Turner2019-01-231-2/+11
* nir: replace more nir_load_system_value calls with builder functionsKarol Herbst2019-01-211-2/+1
* nir: rename nir_var_function to nir_var_function_tempKarol Herbst2019-01-191-7/+7
* intel/fs: Promote execution type to 32-bit when any half-float conversion is ...Francisco Jerez2019-01-181-0/+21
* intel/fs: Don't touch accumulator destination while applying regioning alignm...Jason Ekstrand2019-01-181-1/+23
* intel/eu: Stop overriding exec sizes in send_indirect_messageJason Ekstrand2019-01-181-3/+0
* i965: Drop mark_surface_used mechanism.Kenneth Graunke2019-01-137-100/+0
* intel/nir: Call nir_opt_deref in brw_nir_optimizeJason Ekstrand2019-01-121-0/+1
* intel/peephole_ffma: Fix swizzle propagationJason Ekstrand2019-01-111-4/+7
* i965: Compile fp64 software routines and lower double-opsMatt Turner2019-01-091-22/+70
* intel/compiler: Heap-allocate temporary storageMatt Turner2019-01-091-3/+5
* intel/compiler: Expand size of the 'nr' fieldMatt Turner2019-01-091-4/+3
* intel/compiler: Prevent warnings in the following patchMatt Turner2019-01-0911-36/+38
* intel/compiler: Rearrange code to avoid future problemsMatt Turner2019-01-091-3/+4
* intel/compiler: Avoid false positive assertionsMatt Turner2019-01-091-6/+6
* intel/compiler: Split 64-bit MOV-indirects if neededMatt Turner2019-01-091-1/+2
* intel/compiler: Lower 64-bit MOV/SEL operationsMatt Turner2019-01-091-1/+49
* intel/fs: Remove FS_OPCODE_UNPACK_HALF_2x16_SPLIT opcodes.Francisco Jerez2019-01-096-47/+4
* intel/fs: Remove nasty open-coded CHV/BXT 64-bit workarounds.Francisco Jerez2019-01-092-145/+12
* intel/fs: Remove existing lower_conversions pass.Francisco Jerez2019-01-094-138/+1
* intel/fs: Introduce regioning lowering pass.Francisco Jerez2019-01-095-19/+417
* intel/fs: Constify fs_inst::can_do_source_mods().Francisco Jerez2019-01-092-2/+2
* intel/fs: Respect CHV/BXT regioning restrictions in copy propagation pass.Francisco Jerez2019-01-092-0/+38
* intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.Francisco Jerez2019-01-091-7/+4
* intel/fs: Fix bug in lower_simd_width while splitting an instruction which wa...Francisco Jerez2019-01-091-2/+5
* intel/fs: Implement quad swizzles on ICL+.Francisco Jerez2019-01-093-18/+97
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