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path: root/src/intel/compiler/brw_vec4.cpp
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* intel/compiler: silence unitialized variable warning in opt_vector_float()Brian Paul2019-03-081-1/+1
* intel/compiler: Re-prefix non-logical surface opcodes with VEC4Jason Ekstrand2019-02-281-6/+6
* intel/compiler: Drop unused surface opcodesJason Ekstrand2019-02-281-6/+0
* intel/compiler: Prevent warnings in the following patchMatt Turner2019-01-091-5/+7
* i965/fs: Eliminate unary op on operand of compare-with-zeroIan Romanick2018-12-171-12/+0
* i965: Do NIR shader cloning in the caller.Kenneth Graunke2018-11-201-2/+1
* intel: Don't propagate conditional modifiers if a UD source is negatedJason Ekstrand2018-10-101-0/+20
* Replace uses of _mesa_bitcount with util_bitcountDylan Baker2018-09-071-1/+2
* intel/compiler: silence -Wclass-memaccess warningsCaio Marcelo de Oliveira Filho2018-07-181-2/+2
* intel/compiler: Relax mixed type restriction for saturating immediatesIan Romanick2018-07-061-2/+11
* intel/compiler: Silence unused parameter warnings brw_nir.cIan Romanick2018-07-021-1/+1
* intel/fs: Remove program key argument from generator.Francisco Jerez2018-06-281-1/+1
* i965/vec4: Optimize OR with 0 into a MOVIan Romanick2018-06-151-0/+8
* i965/vec4: Don't register coalesce into source of VS_OPCODE_UNPACK_FLAGS_SIMD4X2Ian Romanick2018-06-151-0/+9
* intel: activate the gl_BaseVertex loweringAntia Puentes2018-05-021-6/+1
* intel: emit is_indexed_draw in the same VE than gl_DrawIDAntia Puentes2018-05-021-5/+9
* intel/compiler: Add uses_is_indexed_draw flagAntia Puentes2018-05-021-0/+4
* intel: Handle firstvertex in an identical way to BaseVertexAntia Puentes2018-04-191-0/+1
* intel/compiler: Add a uses_firstvertex flagNeil Roberts2018-04-191-0/+4
* intel/vec4: Set channel_sizes for MOV_INDIRECT sourcesJason Ekstrand2018-03-301-1/+4
* i965/vec4: Fix null destination register in 3-source instructionsIan Romanick2018-03-261-0/+26
* i965: Add negative_equals methodsIan Romanick2018-03-261-0/+7
* i965/fs: Add infrastructure for generating CSEL instructions.Kenneth Graunke2018-03-081-0/+1
* intel: Drop program size pointer from vec4/fs assembly getters.Kenneth Graunke2018-03-021-3/+2
* intel/ir: Allow representing additional flag subregisters in the IR.Francisco Jerez2018-03-021-3/+4
* compiler: tidy up double_inputs_read usesTimothy Arceri2018-01-301-1/+1
* i965: Drop support for the legacy SNORM -> Float equation.Kenneth Graunke2018-01-021-5/+2
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-1/+1
* i965/vec4: fix splitting of interleaved attributesIago Toral Quiroga2017-11-241-1/+6
* intel/compiler: Remove final_program_size from brw_compile_*Jordan Justen2017-10-311-4/+2
* intel/compiler: add new field for storing program sizeCarl Worth2017-10-311-0/+1
* i965: remove unused variableEric Engestrom2017-10-301-3/+0
* i965: Delete unused brw_vs_prog_data::nr_attributes field.Kenneth Graunke2017-10-271-1/+0
* intel: Allocate prog_data::[pull_]param deeper inside the compilerJason Ekstrand2017-10-121-2/+1
* intel: Rewrite the world of push/pull paramsJason Ekstrand2017-10-121-10/+7
* i965/vec4: Use 'class' src_reg, rather than 'struct' src_regMatt Turner2017-08-211-1/+1
* i965: Move brw_reg_type_letters() as wellMatt Turner2017-08-211-2/+2
* i965: Reorder brw_reg_type enum valuesMatt Turner2017-08-211-1/+2
* i965: Push UBO data, but don't use it just yet.Kenneth Graunke2017-07-131-0/+3
* intel: compiler/i965: fix is_broxton checksLionel Landwerlin2017-06-201-1/+1
* i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3Anuj Phogat2017-06-091-2/+9
* i965/vec4: load dvec3/4 uniforms first in the push constant bufferSamuel Iglesias Gonsálvez2017-05-181-27/+80
* i965/vec4: Use NIR to do GS input remappingJason Ekstrand2017-05-091-60/+0
* i965/vec4: Use NIR remapping for VS attributesJason Ekstrand2017-05-091-36/+24
* intel/compiler/vs: Move inputs_read handling to generic codeJason Ekstrand2017-05-091-0/+3
* i965/vec4: Set VERT_BIT_EDGEFLAG based on the VUE mapJason Ekstrand2017-05-091-0/+11
* i965/vs: Set uses_vertexid and friends from brw_compile_vsJason Ekstrand2017-05-091-0/+17
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-091-10/+10
* i965/vec4: fix register width for DF VGRF and UNIFORMSamuel Iglesias Gonsálvez2017-05-031-5/+7
* i965/vec4: fix vertical stride to avoid breaking region parameter ruleSamuel Iglesias Gonsálvez2017-05-031-18/+32
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