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path: root/src/intel/compiler/brw_shader.cpp
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* intel/compiler: support negate and abs of half float immediatesJose Maria Casanova Crespo2018-05-031-2/+4
* intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediateJose Maria Casanova Crespo2018-05-031-4/+8
* i965: Add negative_equals methodsIan Romanick2018-03-261-0/+6
* compiler: int8/uint8 supportKarol Herbst2018-03-141-0/+4
* intel/fs: Add support for subgroup quad operationsJason Ekstrand2018-03-071-0/+2
* intel/fs: Add a couple of simple helper opcodesJason Ekstrand2018-03-071-0/+5
* i965/fs: Add support for nir_intrinsic_shuffleJason Ekstrand2018-03-071-0/+2
* intel: Drop program size pointer from vec4/fs assembly getters.Kenneth Graunke2018-03-021-3/+2
* intel/compiler: Add Gen11+ native float typeMatt Turner2018-02-281-0/+6
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-6/+3
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-061-0/+6
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-061-0/+7
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-061-0/+4
* i965: Support for 16-bit base types in helper functionsJose Maria Casanova Crespo2017-12-061-0/+6
* i965: Use nir_lower_atomics_to_ssbos and delete ABO compiler code.Kenneth Graunke2017-11-151-32/+0
* intel/compiler: Move the destructor from vec4_visitor to backend_shaderJason Ekstrand2017-11-071-0/+4
* intel/compiler: Add some restrictions to MOV_INDIRECT and BROADCASTJason Ekstrand2017-11-071-0/+2
* intel/compiler: Remove final_program_size from brw_compile_*Jordan Justen2017-10-311-4/+2
* intel/compiler: add new field for storing program sizeCarl Worth2017-10-311-4/+8
* glsl: Remove ir_binop_greater and ir_binop_lequal expressionsIan Romanick2017-10-301-4/+0
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-201-1/+1
* i965: Move fs_inst::has_side_effects()'s eot check to the parent class.Kenneth Graunke2017-10-191-1/+1
* i965/cnl: Make URB {VS, GS, HS, DS} sizes non multiple of 3Anuj Phogat2017-06-091-0/+8
* nir: Embed the shader_info in the nir_shader againJason Ekstrand2017-05-091-14/+14
* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-141-2/+6
* i965: expose BRW_OPCODE_[F32TO16/F16TO32] name on gen8+Alejandro Piñeiro2017-03-291-0/+9
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+1273
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