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path: root/src/intel/compiler/brw_eu_emit.c
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* intel/fs: Don't unnecessarily fall back to indirect sends on Gen12Jason Ekstrand2020-01-241-3/+4
* intel/compiler: Move Gen4/5 rounding to visitorMatt Turner2020-01-221-30/+2
* intel/compiler: Don't change hstride if not neededIván Briano2019-11-181-5/+6
* intel/compiler: Set bits according to source fileSagar Ghuge2019-10-211-2/+12
* intel/compiler: Add Immediate support for 3 source instructionSagar Ghuge2019-10-211-21/+32
* intel/eu: Don't set notify descriptor field of gateway barrier message.Francisco Jerez2019-10-111-1/+0
* intel/eu/gen12: Set SWSB annotations in hand-crafted assembly.Francisco Jerez2019-10-111-5/+52
* intel/eu/gen12: Add tracking of default SWSB state to the current brw_codegen...Francisco Jerez2019-10-111-0/+2
* intel/fs/gen12: Add codegen support for the SYNC instruction.Francisco Jerez2019-10-111-3/+5
* intel/eu/gen12: Don't set thread control, it's gone.Francisco Jerez2019-10-111-2/+4
* intel/eu/gen12: Don't set DD control, it's gone.Francisco Jerez2019-10-111-2/+4
* intel/eu/gen12: Use SEND instruction for split sends.Francisco Jerez2019-10-111-1/+1
* intel/eu/gen12: Codegen SEND descriptor regions correctly.Francisco Jerez2019-10-111-3/+8
* intel/eu/gen12: Codegen pathological SEND source and destination regions.Francisco Jerez2019-10-111-7/+39
* intel/eu/gen12: Codegen control flow instructions correctly.Francisco Jerez2019-10-111-6/+9
* intel/eu/gen12: Codegen three-source instruction source and destination regions.Francisco Jerez2019-10-111-24/+41
* intel/eu/gen12: Fix codegen of immediate source regions.Francisco Jerez2019-10-111-1/+1
* intel/eu: Encode and decode native instruction opcodes from/to IR opcodes.Francisco Jerez2019-10-111-0/+5
* intel/eu: Split brw_inst ex_desc accessors for SEND(C) vs. SENDS(C).Francisco Jerez2019-10-111-1/+1
* i965/fs/generator: refactor rounding mode helper in preparation for float con...Samuel Iglesias Gonsálvez2019-09-171-31/+21
* intel/compiler: Handle bits 15:12 in brw_send_indirect_split_message()Kenneth Graunke2019-08-271-2/+12
* intel/compiler: Fix src0/desc setter orderingKenneth Graunke2019-08-271-2/+2
* intel/fs: Add support for SLM fence in Gen11Caio Marcelo de Oliveira Filho2019-07-111-4/+9
* intel/compiler: Enable the emission of ROR/ROL instructionsSagar Ghuge2019-07-011-0/+2
* intel/compiler: Fix assertions in brw_alu3Sagar Ghuge2019-06-031-3/+3
* intel/fs: Do a stalling MFENCE in endInvocationInterlock()Jason Ekstrand2019-05-301-2/+6
* intel/fs,vec4: Use g0 as the header for MFENCEJason Ekstrand2019-05-301-4/+5
* intel/eu: force stride of 2 on NULL register for Byte instructionsIago Toral Quiroga2019-04-181-0/+11
* intel/compiler: set correct precision fields for 3-source float instructionsIago Toral Quiroga2019-04-181-0/+16
* intel/compiler: allow half-float on 3-source instructions since gen8Iago Toral Quiroga2019-04-181-1/+2
* intel/compiler: handle extended math restrictions for half-floatIago Toral Quiroga2019-04-181-2/+4
* intel/vec4: Drop dead code for handling typed surface messagesJason Ekstrand2019-02-281-89/+0
* intel/eu: Add an EOT parameter to send_indirect_[split]_messageJason Ekstrand2019-02-251-10/+15
* intel/eu: Add support for the SENDS[C] messagesJason Ekstrand2019-01-291-5/+136
* intel/inst: Indent some codeJason Ekstrand2019-01-291-177/+183
* intel/fs: Use SHADER_OPCODE_SEND for surface messagesJason Ekstrand2019-01-291-72/+0
* intel/eu: Rework surface descriptor helpersJason Ekstrand2019-01-291-234/+21
* intel/eu: Add has_simd4x2 bools to surface_write functionsJason Ekstrand2019-01-291-6/+8
* intel/fs: Take an explicit exec size in brw_surface_payload_size()Jason Ekstrand2019-01-291-20/+39
* intel/compiler: Reset default flag register in brw_find_live_channel()Matt Turner2019-01-231-2/+11
* intel/eu: Stop overriding exec sizes in send_indirect_messageJason Ekstrand2019-01-181-3/+0
* intel/compiler: Avoid false positive assertionsMatt Turner2019-01-091-6/+6
* intel/eu/gen7: Fix brw_MOV() with DF destination and strided source.Francisco Jerez2019-01-091-7/+4
* intel/compiler: Set swizzle to BRW_SWIZZLE_XXXX for scalar regionSagar Ghuge2018-12-101-1/+18
* intel/compiler: Change src1 reg type to unsigned doublewordSagar Ghuge2018-10-231-1/+1
* intel/compiler: Implement untyped atomic float min, max, and compare-swap dat...Ian Romanick2018-08-221-0/+47
* intel/eu: Assert that the instruction is send-like in brw_set_desc_ex().Francisco Jerez2018-07-091-2/+3
* intel/eu: Get rid of the return value of brw_send_indirect_message().Francisco Jerez2018-07-091-14/+3
* intel/eu: Get rid of the return value of brw_send_indirect_surface_message().Francisco Jerez2018-07-091-10/+6
* intel/eu: Use descriptor constructors for dataport typed surface messages.Francisco Jerez2018-07-091-47/+35
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