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path: root/src/intel/compiler/brw_eu_defines.h
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* intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+Jason Ekstrand2019-01-291-1/+0
* intel/fs: Use a logical opcode for IMAGE_SIZEJason Ekstrand2019-01-291-0/+1
* intel/fs: Add a generic SEND opcodeJason Ekstrand2019-01-291-0/+7
* intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITSJason Ekstrand2019-01-291-2/+2
* intel/fs: Remove FS_OPCODE_UNPACK_HALF_2x16_SPLIT opcodes.Francisco Jerez2019-01-091-2/+0
* intel/fs: Support min_lod parameters on texture instructionsJason Ekstrand2018-12-111-0/+2
* intel: Use TXS for image_size when we have a typed surfaceJason Ekstrand2018-08-291-0/+2
* intel/compiler: Implement untyped atomic float min, max, and compare-swap dat...Ian Romanick2018-08-221-1/+11
* intel/ir: Uncomment definition of several unused hardware opcodes.Francisco Jerez2018-07-091-14/+14
* intel/eu: Define SET_BITS helper more easily reusable than SET_FIELD.Francisco Jerez2018-07-091-0/+7
* intel/fs: Get rid of MOV_DISPATCH_TO_FLAGSJason Ekstrand2018-06-281-1/+0
* i965: Add ARB_fragment_shader_interlock support.Plamena Manolova2018-06-011-0/+2
* intel/fs: Replace the CINTERP opcode with a simple MOVFrancisco Jerez2018-05-291-1/+0
* intel/fs: Add support for subgroup quad operationsJason Ekstrand2018-03-071-0/+5
* intel/fs: Add a couple of simple helper opcodesJason Ekstrand2018-03-071-0/+13
* i965/fs: Add support for nir_intrinsic_shuffleJason Ekstrand2018-03-071-0/+9
* i965: Combine {VS,FS}_OPCODE_GET_BUFFER_SIZE opcodes.Kenneth Graunke2017-12-301-3/+2
* i965/fs: Add byte scattered read message and fs supportJose Maria Casanova Crespo2017-12-061-0/+2
* i965/fs: Add byte scattered write message and fs supportJose Maria Casanova Crespo2017-12-061-0/+20
* i965/fs: Add remove_extra_rounding_modes optimizationAlejandro Piñeiro2017-12-061-0/+1
* i965/fs: Define new shader opcode to set rounding modesAlejandro Piñeiro2017-12-061-0/+16
* i965: Add align1 ternary instruction disassembler supportMatt Turner2017-10-201-11/+0
* i965: Add align1 ternary instruction field encodingsMatt Turner2017-10-201-0/+35
* i965: Hide the register type hardware encodingsMatt Turner2017-08-211-31/+0
* i965: Use separate enums for register vs immediate typesMatt Turner2017-08-211-18/+30
* i965: Move SF compilation to the compilerJason Ekstrand2017-05-261-0/+2
* i965: Move enums to brw_compiler.h.Rafael Antognolli2017-05-031-21/+0
* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-141-1/+3
* intel: fix compiler buildIago Toral Quiroga2017-03-131-0/+7
* i965: Move the back-end compiler to src/intel/compilerJason Ekstrand2017-03-131-0/+1246
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