| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | intel/icl: Set way_size_per_bank to 4 | Anuj Phogat | 2018-11-26 | 1 | -1/+2 |
| * | i965/icl: Fix L3 configurations | Anuj Phogat | 2018-11-26 | 1 | -6/+6 |
| * | intel/common/icl: Add L3 config | Anuj Phogat | 2018-03-22 | 1 | -0/+18 |
| * | intel/l3: Don't allocate SLM partition on ICL+. | Francisco Jerez | 2018-03-02 | 1 | -1/+1 |
| * | i965/cnl: Add l3 configuration for Cannonlake | Ben Widawsky | 2017-06-20 | 1 | -1/+20 |
| * | i965: Add a variable for way size per bank in get_l3_way_size() | Anuj Phogat | 2017-06-20 | 1 | -5/+4 |
| * | i965: Fix broxton 2x6 l3 config | Anuj Phogat | 2017-06-20 | 1 | -0/+16 |
| * | i965/cnl: Handle gen10 in switch cases across the driver | Anuj Phogat | 2017-06-09 | 1 | -0/+1 |
| * | intel: Fix broxton 2x6 way size computation | Anuj Phogat | 2017-06-06 | 1 | -0/+4 |
| * | i965: Simplify l3 way size computations | Anuj Phogat | 2017-06-02 | 1 | -10/+2 |
| * | i965/l3: Add explicit way size calculation for bxt | Ben Widawsky | 2016-10-05 | 1 | -1/+3 |
| * | intel: Pull the guts of gen7_l3_state.c into a shared helper | Jason Ekstrand | 2016-09-03 | 1 | -0/+304 |
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