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* gallium: Remove util_format_s3tc_init()Matt Turner2017-10-0214-98/+5
* gallium: Remove util_format_s3tc_enabledMatt Turner2017-10-0214-110/+3
* gallium/u_tests: test sync_file fencesMarek Olšák2017-10-031-0/+101
* freedreno/a5xx: fix missing restore stateRob Clark2017-10-021-0/+3
* swr/rast: do not crash on NULL strings returned by getenvEmil Velikov2017-10-021-1/+2
* freedreno/a5xx: align height to GMEMRob Clark2017-10-021-1/+5
* radeonsi: adjust clip discard based on line width / point sizeNicolai Hähnle2017-10-023-11/+27
* radeonsi: remove si_context::{scissor_enabled,clip_halfz}Nicolai Hähnle2017-10-023-26/+24
* radeonsi: simplify the signature of si_update_vs_writes_viewport_indexNicolai Hähnle2017-10-023-7/+6
* radeonsi: move current_rast_prim into si_contextNicolai Hähnle2017-10-026-15/+11
* radeonsi: move and rename scissor and viewport state and functionsNicolai Hähnle2017-10-0210-182/+184
* radeonsi: remove si_apply_scissor_bug_workaroundNicolai Hähnle2017-10-022-19/+0
* radeonsi: move r600_viewport.c to si_viewport.cNicolai Hähnle2017-10-023-2/+2
* radeonsi: fix maximum advertised point size / line widthNicolai Hähnle2017-10-022-8/+3
* radeonsi: deduce rast_prim correctly for tessellation point modeNicolai Hähnle2017-10-021-3/+6
* radeonsi: don't discard points and linesNicolai Hähnle2017-10-022-2/+26
* radeonsi: move current_rast_prim to r600_common_contextNicolai Hähnle2017-10-025-9/+13
* gallium: add PIPE_FORMAT_R10G10B10X2_UNORMNicolai Hähnle2017-10-024-0/+10
* freedreno: fix PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVERob Clark2017-10-022-4/+5
* radeonsi: fix a regression in integer cube map handlingNicolai Hähnle2017-10-021-8/+26
* amd/common: move ac_build_phi from radeonsiNicolai Hähnle2017-10-021-17/+3
* radeonsi: don't use the template keywordMarek Olšák2017-09-301-7/+7
* gallium/vl: don't use the template keywordMarek Olšák2017-09-301-14/+14
* radeonsi/uvd: clean up si_video_buffer_createBenedikt Schemmer2017-09-301-30/+17
* radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bbMarek Olšák2017-09-301-3/+8
* gallium: add new LOD opcodeRoland Scheidegger2017-09-305-5/+74
* st/va: add dst rect to avoid scale on deintLeo Liu2017-09-291-6/+6
* radeonsi: emit DLDEXP and DFRACEXP TGSI opcodesNicolai Hähnle2017-09-292-1/+26
* radeonsi: emit LDEXP opcodeNicolai Hähnle2017-09-292-1/+3
* gallium: add LDEXP TGSI instruction and corresponding capNicolai Hähnle2017-09-2920-3/+50
* tgsi: infer that dst[1] of DFRACEXP is an integerNicolai Hähnle2017-09-295-6/+9
* gallivm: add support for TGSI instructions with two outputsNicolai Hähnle2017-09-293-1/+31
* gallivm: add dst register index to lp_build_tgsi_context::emit_storeNicolai Hähnle2017-09-296-20/+27
* tgsi: clarify the semantics of DFRACEXPNicolai Hähnle2017-09-294-22/+20
* tgsi: fix the documentation of DLDEXPNicolai Hähnle2017-09-291-1/+1
* tgsi: infer that DLDEXP's second source has an integer typeNicolai Hähnle2017-09-294-7/+11
* r600: cleanup set_occlusion_query_stateNicolai Hähnle2017-09-293-14/+3
* r300: add missing case PIPE_SHADER_CAP_INT64_ATOMICSNicolai Hähnle2017-09-291-0/+1
* radeonsi: fix border color translation for integer texturesNicolai Hähnle2017-09-293-29/+60
* radeonsi: clamp border colors for upgraded depth texturesNicolai Hähnle2017-09-291-59/+60
* radeonsi: clamp depth comparison value only for fixed point formatsNicolai Hähnle2017-09-296-14/+53
* radeonsi/gfx9: fix geometry shaders without output verticesNicolai Hähnle2017-09-291-3/+5
* radeonsi: move descriptor logs to after corresponding draw/compute packetNicolai Hähnle2017-09-292-8/+6
* amd/common: remove ac_shader_abi::chip_classNicolai Hähnle2017-09-291-2/+0
* gallium/radeon: fix a commentNicolai Hähnle2017-09-291-1/+1
* svga: add missing PIPE_SHADER_CAP_INT64_ATOMICS switch casesBrian Paul2017-09-281-0/+2
* svga: trivial whitespace clean-ups in svga_screen.cBrian Paul2017-09-281-11/+13
* gallium/util: use new util_vasprintf() functionBrian Paul2017-09-281-1/+2
* svga: start advertising PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTIONNeha Bhende2017-09-281-1/+3
* etnaviv: optimize RS transfersLucas Stach2017-09-281-4/+25
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