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* nv50,nvc0: fix integer MS resolves using 2d engineIlia Mirkin2018-02-221-1/+2
| | | | | | | | We don't want filtering for integer textures, same as depth/stencil. Fixes: KHR-GL45.direct_state_access.renderbuffers_storage_multisample Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Karol Herbst <[email protected]>
* nvc0: fix writing query results into bufferIlia Mirkin2018-02-221-4/+10
| | | | | | | | | | | We need to mark the range as valid, and validate the resource using a helper to ensure that the buffer status is marked properly. Fixes some CTS pipeline stats query tests, and KHR-GL45.direct_state_access.queries_functional Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Karol Herbst <[email protected]>
* nv50,nvc0: fix clear buffer accelerationIlia Mirkin2018-02-222-28/+17
| | | | | | | | | | | | Two things were off: - valid range was not updated, which could affect waiting for future maps - fencing was done manually instead of using the *_resource_validate helper, which resulted in a missed dirty buffer flag being set Fixes: KHR-GL45.direct_state_access.buffers_clear Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Karol Herbst <[email protected]>
* glx: Properly handle cases where screen creation failsChuck Atkins2018-02-223-30/+33
| | | | | | | | | | | | | This fixes a segfault exposed by a29d63ecf7 which occurs when swr is used on an unsupported architecture. v2: re-work to place logic in xmesa_init_display Signed-off-by: Chuck Atkins <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Cc: [email protected] Cc: George Kyriazis <[email protected]> Cc: Bruce Cherniak <[email protected]>
* radeonsi/nir: collect more accurate output_usagemaskTimothy Arceri2018-02-221-13/+43
| | | | | | | | | | | Fixes assert in the glsl-1.50-gs-max-output-components piglit test. Note that the double handling will only work for doubles that don't take up multiple slots i.e. double and dvec2. However dual slot double handling is an existing bug which is made no worse by this patch. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: disable GLSL IR loop unrollingTimothy Arceri2018-02-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Delaying unrolling and allowing NIR to do it instead has been shown to result in better code in drivers such as i965. shader-db results appear to show the same is true for radeonsi. The other advantage is that using NIR unrolling improves compile times significantly. Totals from affected shaders: SGPRS: 9624 -> 10016 (4.07 %) VGPRS: 6800 -> 6464 (-4.94 %) Spilled SGPRs: 0 -> 2 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 359176 -> 332264 (-7.49 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 1355 -> 1432 (5.68 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: fix tess varying loads for doublesTimothy Arceri2018-02-221-2/+2
| | | | | | | | | Fixes the following piglit tests: tests/spec/arb_tessellation_shader/execution/double-array-vs-tcs-tes.shader_test tests/spec/arb_tessellation_shader/execution/double-vs-tcs-tes.shader_test Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: pass type to load_tess_varyings()Timothy Arceri2018-02-222-0/+3
| | | | | | We need this to be able to load 64bit varyings. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: don't flush when si_eliminate_fast_color_clear is no-opMarek Olšák2018-02-211-1/+5
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* radeonsi: make texture_discard_cmask/eliminate functions non-staticMarek Olšák2018-02-212-11/+13
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* radeonsi: enable uvd encode for HEVC mainJames Zhu2018-02-211-1/+3
| | | | | | | Enable UVD encode for HEVC main profile Signed-off-by: James Zhu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* radeonsi:create uvd hevc enc entryJames Zhu2018-02-211-3/+12
| | | | | | | Add UVD hevc encode pipe video codec creation entry Signed-off-by: James Zhu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* radeon/uvd:add uvd hevc enc functionsJames Zhu2018-02-213-0/+383
| | | | | | | Implement UVD hevc encode functions Signed-off-by: James Zhu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* radeon/uvd:add uvd hevc enc hw ib implementationJames Zhu2018-02-213-0/+1134
| | | | | | | Implement required IBs for UVD HEVC encode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* radeon/uvd:add uvd hevc enc hw interface headerJames Zhu2018-02-213-0/+471
| | | | | | | Add hevc encode hardware interface for UVD Signed-off-by: James Zhu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* winsys/amdgpu:add uvd hevc enc support in amdgpu csJames Zhu2018-02-211-0/+6
| | | | | | | Support UVD HEVC encode in amdgpu cs Signed-off-by: James Zhu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* nvir/nvc0: fix legalizing of ld unlock c0[0x10000]Karol Herbst2018-02-211-1/+1
| | | | | | | | | We have to increase the file index also for 0x10000 not just for values greater than 0x10000. Fixes: 37b67db6ae34fb6586d640a7a1b6232f091dd812 Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno/ir3: fix use_count refcnt'ing issueRob Clark2018-02-201-0/+1
| | | | | | | | | | Was hitting an assert with vs-varying-array-mat4-index-col-row-wr.shader_test When eliminating a copy, we were dropping the use_count of the mov that is skipped, but not increasing the use_count of it's src instruction. Fixes: 76440fcca91 freedreno/ir3: clean up dangling false-dep's Signed-off-by: Rob Clark <[email protected]>
* svga: replaced 'unsigned' with proper enum types in shader codeBrian Paul2018-02-201-12/+21
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* swr: bump minimum supported LLVM version to 4.0Andres Gomez2018-02-202-3/+3
| | | | | | | | | | | | | | | | | | Since radv and radeonsi removed support for LLVM 3.9 the distcheck target got broken because SWR distribution needed 3.9.x. After checking with George Kyriazis, SWR is OK with moving to LLVM 4.0 and above, which will solve this problem. Fixes: 3bf1e036e8a ("amd: remove support for LLVM 3.9") Cc: George Kyriazis <[email protected]> Cc: Tim Rowley <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Dylan Baker <[email protected]> Cc: Eric Engestrom <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: George Kyriazis <[email protected]>
* svga: Fix a leftover debug hackThomas Hellstrom2018-02-201-2/+2
| | | | | | | | | | | | | | | Fix what appears to be a leftover debug hack. The hack would force the driver to take a different blit path; possibly, although unverified, reverting to software blits. Tested using piglit tests/quick. No related regressions. Cc: "17.2 17.3 18.0" <[email protected]> Fixes: 9d81ab7376 (svga: Relax the format checks for copy_region_vgpu10 somewhat) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104625 Reported-by: Grazvydas Ignotas <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nv50,nvc0: mark ABGR format as displayable instead of ARGB formatIlia Mirkin2018-02-191-2/+2
| | | | | | This matches the hardware's capabilities. Signed-off-by: Ilia Mirkin <[email protected]>
* st/dri: only expose config formats that are display targetsIlia Mirkin2018-02-191-1/+2
| | | | | | | | | In the case of NVIDIA hardware, ABGR is displayable but ARGB is not. Only advertise the one set in the visuals list. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Daniel Stone <[email protected]>
* mesa: add xbgr support adjacent to xrgbIlia Mirkin2018-02-193-1/+55
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Acked-by: Daniel Stone <[email protected]>
* radeonsi: add nir shader cache supportTimothy Arceri2018-02-201-11/+30
| | | | | | | In future we might want to try avoid calling nir_serialize() but this works for now. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rename variables tgsi_binary -> ir_binaryTimothy Arceri2018-02-201-21/+21
| | | | | | This better represents that the ir could be either tgsi or nir. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix regression from 32-bit pointers on CIMarek Olšák2018-02-191-1/+1
| | | | Tested-by: Michel Dänzer <[email protected]>
* radeonsi/nir: fix gl_FragCoord for pixel_center_integerTimothy Arceri2018-02-191-0/+5
| | | | | | Fixes piglit test glsl-arb-fragment-coord-conventions Reviewed-by: Kenneth Graunke <[email protected]>
* gm107/ir: avoid using kepler instruction capabilitiesIlia Mirkin2018-02-172-21/+45
| | | | | | | | Split up the op properties table into generation-specific bits, and only use the kepler ones on kepler. Fixes some CTS images tests. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]>
* nvc0: add support for bindless on maxwell+Ilia Mirkin2018-02-173-14/+116
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: change how SUQ works in preparation for bindlessIlia Mirkin2018-02-173-1/+61
| | | | | | | All this information can be retrieved from the TIC directly. Avoid having to dip into the constbuf information about the image. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: Use GP100_COMPUTE_CLASS on GP10BMikko Perttunen2018-02-171-1/+2
| | | | | | | | GP10B requires the use of GP100_COMPUTE_CLASS instead of GP104_COMPUTE_CLASS as is used for other non-GP100 chips. Signed-off-by: Mikko Perttunen <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: implement 32-bit pointers in user data SGPRs (v2)Marek Olšák2018-02-175-59/+123
| | | | | | | | | | | | | | | | | | | | | | | | | | User SGPRs changes: VS: 14 -> 9 TCS: 14 -> 10 TES: 10 -> 6 GS: 8 -> 4 GSCOPY: 2 -> 1 PS: 9 -> 5 Merged VS-TCS: 24 -> 16 Merged VS-GS: 18 -> 11 Merged TES-GS: 18 -> 11 SGPRS: 2170102 -> 2158430 (-0.54 %) VGPRS: 1645656 -> 1641516 (-0.25 %) Spilled SGPRs: 9078 -> 8810 (-2.95 %) Spilled VGPRs: 130 -> 114 (-12.31 %) Scratch size: 1508 -> 1492 (-1.06 %) dwords per thread Code Size: 52094872 -> 52692540 (1.15 %) bytes Max Waves: 371848 -> 372723 (0.24 %) v2: - the shader cache needs to take address32_hi into account - set amdgpu-32bit-address-high-bits Reviewed-by: Samuel Pitoiset <[email protected]> (v1)
* radeonsi: disallow constant buffers with a 64-bit address in slot 0Marek Olšák2018-02-172-1/+9
| | | | | | | State trackers must use a user buffer or const_uploader, or set pipe_resource::flags same as const_uploader->flags. Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: move const_uploader allocations to 32-bit address spaceMarek Olšák2018-02-173-2/+7
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/radeon: implement and enable 32-bit VM allocationsMarek Olšák2018-02-173-8/+64
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/radeon: add struct radeon_vm_heapMarek Olšák2018-02-173-36/+47
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: enable 32-bit VM allocationsMarek Olšák2018-02-171-1/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/radeon: add 32-bit address space heapsMarek Olšák2018-02-171-3/+44
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium: use PIPE_CAP_CONSTBUF0_FLAGSMarek Olšák2018-02-174-5/+27
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* gallium: allow drivers to impose BO flags restrictions on constant buffer 0Marek Olšák2018-02-1718-0/+21
| | | | Required by radeonsi for optimal behavior.
* meson: Add Haiku platform support v4Alexander von Gluck IV2018-02-164-0/+119
| | | | Reviewed-by: Dylan Baker <[email protected]>
* meson: freedreno depends on nirDylan Baker2018-02-161-0/+1
| | | | | | | | | This fixes a race condition in building targets that link in freedreno. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105120 Fixes: 0bbecc5a8548883f76a7 ("meson: define driver dependencies") Signed-off-by: Dylan Baker <[email protected]> Acked-by: Mark Janes <[email protected]>
* swr/rast: blend_epi32() should return Integer, not FloatGeorge Kyriazis2018-02-161-1/+1
| | | | | | | fix gcc8 compiler error for KNL. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105029 Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Normalize path for debug metadataGeorge Kyriazis2018-02-161-1/+2
| | | | | | in template gen_llvm.hpp Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Consolidate archrast Draw eventsGeorge Kyriazis2018-02-164-26/+79
| | | | | | | | | | | | | | | | Consolidate archrst draw events into single draw event with an attribute that represents the type of draw - Add handlers for new private proto versions of DrawInstancedEvent, DrawIndexedInstancedEvent, DrawInstancedSplitEvent, and DrawIndexedInstancedSplitEvent - Convert the draw events to generic DrawInfoEvents - parse_proto_event_fields() replaces 'AR_DRAW_TYPE' as a field type with 'uint32_t'. This draw type is actually an enum, but can be represented as an unsigned integer. - is_draw_or_dispatch() recognizes DrawInfoEvent as a draw event Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add semantics for translating addressGeorge Kyriazis2018-02-162-0/+5
| | | | | | Added support for another full translation path in fetch jitter. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Convert C Sampler intrinsicsGeorge Kyriazis2018-02-162-0/+19
| | | | | | | | | | Convert portions of the C sampler to the rasty SIMD lib. Also fix SRL call with a non-immediate. Don't count on the compiler automagically converting an srli call to srl if the shift count isn't an immediate. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Make SIMDLib templated types easier to useGeorge Kyriazis2018-02-165-298/+307
| | | | | | "typename SIMD_T::TypeName" --> "TypeName<SIMD_T>" Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Be more explicit when fetching next componentGeorge Kyriazis2018-02-162-4/+11
| | | | | | | Use a new function to denote that we want to get offset to next component and hide the fact that GEP is used underneath. Reviewed-by: Bruce Cherniak <[email protected]>
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