diff options
author | James Zhu <[email protected]> | 2018-02-06 13:29:11 -0500 |
---|---|---|
committer | Leo Liu <[email protected]> | 2018-02-21 13:53:38 -0500 |
commit | e7d51e27ed4d1fdfbeb5f7cf71304f243021a721 (patch) | |
tree | 5654a4bcf7eae2bbc3cd850e6c4a19a3b3db034a /src/gallium | |
parent | 2b86f5fa0b25dd66a65057362bab1ebf8615c94b (diff) |
radeon/uvd:add uvd hevc enc functions
Implement UVD hevc encode functions
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Boyuan Zhang <[email protected]>
Diffstat (limited to 'src/gallium')
-rw-r--r-- | src/gallium/drivers/radeon/Makefile.sources | 1 | ||||
-rw-r--r-- | src/gallium/drivers/radeon/meson.build | 1 | ||||
-rw-r--r-- | src/gallium/drivers/radeon/radeon_uvd_enc.c | 381 |
3 files changed, 383 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources index 061d1e1d767..f8ee860a663 100644 --- a/src/gallium/drivers/radeon/Makefile.sources +++ b/src/gallium/drivers/radeon/Makefile.sources @@ -16,6 +16,7 @@ C_SOURCES := \ radeon_vcn_enc.c \ radeon_vcn_enc.h \ radeon_uvd_enc_1_1.c \ + radeon_uvd_enc.c \ radeon_uvd_enc.h \ radeon_vce_40_2_2.c \ radeon_vce_50.c \ diff --git a/src/gallium/drivers/radeon/meson.build b/src/gallium/drivers/radeon/meson.build index 1bc5e836c62..582a5ff5e21 100644 --- a/src/gallium/drivers/radeon/meson.build +++ b/src/gallium/drivers/radeon/meson.build @@ -36,6 +36,7 @@ files_libradeon = files( 'radeon_vcn_dec.c', 'radeon_vcn_dec.h', 'radeon_uvd_enc_1_1.c', + 'radeon_uvd_enc.c', 'radeon_uvd_enc.h', 'radeon_vce_40_2_2.c', 'radeon_vce_50.c', diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c b/src/gallium/drivers/radeon/radeon_uvd_enc.c new file mode 100644 index 00000000000..94bd26a08b5 --- /dev/null +++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c @@ -0,0 +1,381 @@ +/************************************************************************** + * + * Copyright 2018 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#include <stdio.h> + +#include "pipe/p_video_codec.h" + +#include "util/u_video.h" +#include "util/u_memory.h" + +#include "vl/vl_video_buffer.h" + +#include "radeonsi/si_pipe.h" +#include "radeon_video.h" +#include "radeon_uvd_enc.h" + +#define UVD_HEVC_LEVEL_1 30 +#define UVD_HEVC_LEVEL_2 60 +#define UVD_HEVC_LEVEL_2_1 63 +#define UVD_HEVC_LEVEL_3 90 +#define UVD_HEVC_LEVEL_3_1 93 +#define UVD_HEVC_LEVEL_4 120 +#define UVD_HEVC_LEVEL_4_1 123 +#define UVD_HEVC_LEVEL_5 150 +#define UVD_HEVC_LEVEL_5_1 153 +#define UVD_HEVC_LEVEL_5_2 156 +#define UVD_HEVC_LEVEL_6 180 +#define UVD_HEVC_LEVEL_6_1 183 +#define UVD_HEVC_LEVEL_6_2 186 + +static void +radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc, + struct pipe_h265_enc_picture_desc *pic) +{ + enc->enc_pic.picture_type = pic->picture_type; + enc->enc_pic.frame_num = pic->frame_num; + enc->enc_pic.pic_order_cnt = pic->pic_order_cnt; + enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type; + enc->enc_pic.not_referenced = pic->not_referenced; + enc->enc_pic.is_iframe = + (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_IDR) + || (pic->picture_type == PIPE_H265_ENC_PICTURE_TYPE_I); + enc->enc_pic.crop_left = 0; + enc->enc_pic.crop_right = + (align(enc->base.width, 16) - enc->base.width) / 2; + enc->enc_pic.crop_top = 0; + enc->enc_pic.crop_bottom = + (align(enc->base.height, 16) - enc->base.height) / 2; + enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag; + enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc; + enc->enc_pic.general_level_idc = pic->seq.general_level_idc; + enc->enc_pic.max_poc = pic->seq.intra_period; + enc->enc_pic.log2_max_poc = 0; + for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++) + i = (i >> 1); + enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc; + enc->enc_pic.pic_width_in_luma_samples = + pic->seq.pic_width_in_luma_samples; + enc->enc_pic.pic_height_in_luma_samples = + pic->seq.pic_height_in_luma_samples; + enc->enc_pic.log2_diff_max_min_luma_coding_block_size = + pic->seq.log2_diff_max_min_luma_coding_block_size; + enc->enc_pic.log2_min_transform_block_size_minus2 = + pic->seq.log2_min_transform_block_size_minus2; + enc->enc_pic.log2_diff_max_min_transform_block_size = + pic->seq.log2_diff_max_min_transform_block_size; + enc->enc_pic.max_transform_hierarchy_depth_inter = + pic->seq.max_transform_hierarchy_depth_inter; + enc->enc_pic.max_transform_hierarchy_depth_intra = + pic->seq.max_transform_hierarchy_depth_intra; + enc->enc_pic.log2_parallel_merge_level_minus2 = + pic->pic.log2_parallel_merge_level_minus2; + enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8; + enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8; + enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type; + enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand; + enc->enc_pic.sample_adaptive_offset_enabled_flag = + pic->seq.sample_adaptive_offset_enabled_flag; + enc->enc_pic.pcm_enabled_flag = 0; /*HW not support PCM */ + enc->enc_pic.sps_temporal_mvp_enabled_flag = + pic->seq.sps_temporal_mvp_enabled_flag; +} + +static void +flush(struct radeon_uvd_encoder *enc) +{ + enc->ws->cs_flush(enc->cs, PIPE_FLUSH_ASYNC, NULL); +} + +static void +radeon_uvd_enc_flush(struct pipe_video_codec *encoder) +{ + struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *) encoder; + flush(enc); +} + +static void +radeon_uvd_enc_cs_flush(void *ctx, unsigned flags, + struct pipe_fence_handle **fence) +{ + // just ignored +} + +static unsigned +get_cpb_num(struct radeon_uvd_encoder *enc) +{ + unsigned w = align(enc->base.width, 16) / 16; + unsigned h = align(enc->base.height, 16) / 16; + unsigned dpb; + + switch (enc->base.level) { + case UVD_HEVC_LEVEL_1: + dpb = 36864; + break; + + case UVD_HEVC_LEVEL_2: + dpb = 122880; + break; + + case UVD_HEVC_LEVEL_2_1: + dpb = 245760; + break; + + case UVD_HEVC_LEVEL_3: + dpb = 552960; + break; + + case UVD_HEVC_LEVEL_3_1: + dpb = 983040; + break; + + case UVD_HEVC_LEVEL_4: + case UVD_HEVC_LEVEL_4_1: + dpb = 2228224; + break; + + case UVD_HEVC_LEVEL_5: + case UVD_HEVC_LEVEL_5_1: + case UVD_HEVC_LEVEL_5_2: + dpb = 8912896; + break; + + case UVD_HEVC_LEVEL_6: + case UVD_HEVC_LEVEL_6_1: + case UVD_HEVC_LEVEL_6_2: + default: + dpb = 35651584; + break; + } + + return MIN2(dpb / (w * h), 16); +} + +static void +radeon_uvd_enc_begin_frame(struct pipe_video_codec *encoder, + struct pipe_video_buffer *source, + struct pipe_picture_desc *picture) +{ + struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *) encoder; + struct vl_video_buffer *vid_buf = (struct vl_video_buffer *) source; + + radeon_uvd_enc_get_param(enc, + (struct pipe_h265_enc_picture_desc *) picture); + + enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma); + enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma); + + enc->need_feedback = false; + + if (!enc->stream_handle) { + struct rvid_buffer fb; + enc->stream_handle = si_vid_alloc_stream_handle(); + enc->si = CALLOC_STRUCT(rvid_buffer); + si_vid_create_buffer(enc->screen, enc->si, 128 * 1024, + PIPE_USAGE_STAGING); + si_vid_create_buffer(enc->screen, &fb, 4096, PIPE_USAGE_STAGING); + enc->fb = &fb; + enc->begin(enc, picture); + flush(enc); + si_vid_destroy_buffer(&fb); + } +} + +static void +radeon_uvd_enc_encode_bitstream(struct pipe_video_codec *encoder, + struct pipe_video_buffer *source, + struct pipe_resource *destination, void **fb) +{ + struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *) encoder; + enc->get_buffer(destination, &enc->bs_handle, NULL); + enc->bs_size = destination->width0; + + *fb = enc->fb = CALLOC_STRUCT(rvid_buffer); + + if (!si_vid_create_buffer(enc->screen, enc->fb, 4096, PIPE_USAGE_STAGING)) { + RVID_ERR("Can't create feedback buffer.\n"); + return; + } + + enc->need_feedback = true; + enc->encode(enc); +} + +static void +radeon_uvd_enc_end_frame(struct pipe_video_codec *encoder, + struct pipe_video_buffer *source, + struct pipe_picture_desc *picture) +{ + struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *) encoder; + flush(enc); +} + +static void +radeon_uvd_enc_destroy(struct pipe_video_codec *encoder) +{ + struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *) encoder; + + if (enc->stream_handle) { + struct rvid_buffer fb; + enc->need_feedback = false; + si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING); + enc->fb = &fb; + enc->destroy(enc); + flush(enc); + si_vid_destroy_buffer(&fb); + } + + si_vid_destroy_buffer(&enc->cpb); + enc->ws->cs_destroy(enc->cs); + FREE(enc); +} + +static void +radeon_uvd_enc_get_feedback(struct pipe_video_codec *encoder, + void *feedback, unsigned *size) +{ + struct radeon_uvd_encoder *enc = (struct radeon_uvd_encoder *) encoder; + struct rvid_buffer *fb = feedback; + + if (NULL != size) { + radeon_uvd_enc_feedback_t *fb_data = + (radeon_uvd_enc_feedback_t *) enc->ws->buffer_map(fb->res->buf, + enc->cs, + PIPE_TRANSFER_READ_WRITE); + + if (!fb_data->status) + *size = fb_data->bitstream_size; + else + *size = 0; + enc->ws->buffer_unmap(fb->res->buf); + } + + si_vid_destroy_buffer(fb); + FREE(fb); +} + +struct pipe_video_codec * +radeon_uvd_create_encoder(struct pipe_context *context, + const struct pipe_video_codec *templ, + struct radeon_winsys *ws, + radeon_uvd_enc_get_buffer get_buffer) +{ + struct si_screen *sscreen = (struct si_screen *) context->screen; + struct r600_common_context *rctx = (struct r600_common_context *) context; + struct radeon_uvd_encoder *enc; + struct pipe_video_buffer *tmp_buf, templat = { }; + struct radeon_surf *tmp_surf; + unsigned cpb_size; + + if (!si_radeon_uvd_enc_supported(sscreen)) { + RVID_ERR("Unsupported UVD ENC fw version loaded!\n"); + return NULL; + } + + enc = CALLOC_STRUCT(radeon_uvd_encoder); + + if (!enc) + return NULL; + + enc->base = *templ; + enc->base.context = context; + enc->base.destroy = radeon_uvd_enc_destroy; + enc->base.begin_frame = radeon_uvd_enc_begin_frame; + enc->base.encode_bitstream = radeon_uvd_enc_encode_bitstream; + enc->base.end_frame = radeon_uvd_enc_end_frame; + enc->base.flush = radeon_uvd_enc_flush; + enc->base.get_feedback = radeon_uvd_enc_get_feedback; + enc->get_buffer = get_buffer; + enc->bits_in_shifter = 0; + enc->screen = context->screen; + enc->ws = ws; + enc->cs = + ws->cs_create(rctx->ctx, RING_UVD_ENC, radeon_uvd_enc_cs_flush, enc); + + if (!enc->cs) { + RVID_ERR("Can't get command submission context.\n"); + goto error; + } + + struct rvid_buffer si; + si_vid_create_buffer(enc->screen, &si, 128 * 1024, PIPE_USAGE_STAGING); + enc->si = &si; + + templat.buffer_format = PIPE_FORMAT_NV12; + templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420; + templat.width = enc->base.width; + templat.height = enc->base.height; + templat.interlaced = false; + + if (!(tmp_buf = context->create_video_buffer(context, &templat))) { + RVID_ERR("Can't create video buffer.\n"); + goto error; + } + + enc->cpb_num = get_cpb_num(enc); + + if (!enc->cpb_num) + goto error; + + get_buffer(((struct vl_video_buffer *) tmp_buf)->resources[0], NULL, + &tmp_surf); + + cpb_size = (sscreen->info.chip_class < GFX9) ? + align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) * + align(tmp_surf->u.legacy.level[0].nblk_y, 32) : + align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * + align(tmp_surf->u.gfx9.surf_height, 32); + + cpb_size = cpb_size * 3 / 2; + cpb_size = cpb_size * enc->cpb_num; + tmp_buf->destroy(tmp_buf); + + if (!si_vid_create_buffer + (enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) { + RVID_ERR("Can't create CPB buffer.\n"); + goto error; + } + + radeon_uvd_enc_1_1_init(enc); + + return &enc->base; + + error: + if (enc->cs) + enc->ws->cs_destroy(enc->cs); + + si_vid_destroy_buffer(&enc->cpb); + + FREE(enc); + return NULL; +} + +bool +si_radeon_uvd_enc_supported(struct si_screen * sscreen) +{ + return (sscreen->info.uvd_enc_supported); +} |