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* st/xlib: remove always true ifdef GLX_EXTENSION guardsEmil Velikov2017-02-131-6/+0
* vl: remove DRI2DriverPrimeShift compile guardsEmil Velikov2017-02-131-2/+0
* winsys/intel: remove unused winsys - ilo was its only userEmil Velikov2017-02-135-744/+0
* nv50,nvc0: use alternate samplers for stencilIlia Mirkin2017-02-121-3/+3
* etnaviv: Set shader instruction area correctly for GC3000Wladimir J. van der Laan2017-02-121-5/+21
* etnaviv: Update hw header filesWladimir J. van der Laan2017-02-125-48/+160
* nvc0: set the render condition in the compute objectIlia Mirkin2017-02-111-2/+10
* gm107/ir: fix address offset bitfield for ATOMSIlia Mirkin2017-02-111-1/+1
* nv50/ir: convert an ATOM.EXCH without a destination into a storeIlia Mirkin2017-02-111-0/+5
* nvc0: fix 64-bit integer query buffer writesIlia Mirkin2017-02-113-20/+37
* nv50/ir: return a register when retrieving thread id sysvalIlia Mirkin2017-02-111-1/+1
* nv50/ir: add missing break after DSSGIlia Mirkin2017-02-111-0/+1
* etnaviv: shader-db tracesChristian Gmeiner2017-02-114-1/+47
* etnaviv: keep track of emitted loopsChristian Gmeiner2017-02-112-0/+7
* etnaviv: wire up core pipe_debug_callbackChristian Gmeiner2017-02-112-0/+15
* vc4: Enable glSampleMask() even when !rasterizer->multisample.Eric Anholt2017-02-101-2/+1
* vc4: Respect glSampleMask() even when we're not writing color.Eric Anholt2017-02-101-3/+13
* vc4: Use the nir_builder helper for loading sample mask.Eric Anholt2017-02-101-10/+1
* vc4: Use accurate 1/w in coordinate shader as well as vert shader.Eric Anholt2017-02-101-1/+1
* vc4: Drop VS inputs to 8.Eric Anholt2017-02-101-4/+1
* vc4: Avoid emitting small immediates for UBO indirect load address guards.Eric Anholt2017-02-105-4/+20
* st/nine: update configure options in the READMEEmil Velikov2017-02-101-2/+1
* gallium/radeon: use staging for texture read mappings from GTT WCMarek Olšák2017-02-101-4/+5
* gallium/radeon: ignore the level parameter in buffer_transfer_mapMarek Olšák2017-02-101-5/+4
* gallium/radeon: fix performance of buffer readbacksMarek Olšák2017-02-101-8/+9
* radeonsi: align vertex buffer descriptor list size for optimal prefetchMarek Olšák2017-02-104-2/+7
* radeonsi: align shader binaries to CP DMA alignment for optimal prefetchMarek Olšák2017-02-101-1/+2
* radeonsi: move CP_DMA_ALIGNMENT definitionMarek Olšák2017-02-102-10/+10
* radeonsi: remove SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFERMarek Olšák2017-02-103-6/+6
* radeonsi: remove separate CB/DB_META flush flagsMarek Olšák2017-02-103-17/+8
* radeonsi: reduce the number of FMASK input coordinatesMarek Olšák2017-02-101-7/+3
* radeonsi: write shader asm annotated with wave info into GPU hang reportsMarek Olšák2017-02-103-3/+252
* radeonsi: write wave information into GPU hang reportsMarek Olšák2017-02-101-0/+20
* tgsi-dump: dump label if instruction has oneMarc-André Lureau2017-02-101-11/+13
* tgsi: remove ureg_label_insnMarc-André Lureau2017-02-102-38/+0
* nvc0/ir: fix ubo max clamp, reset file indexIlia Mirkin2017-02-091-1/+3
* nv50/ir: always return 0 when trying to read thread id along unit dimIlia Mirkin2017-02-094-5/+17
* nvc0/ir: fix robustness guarantees for constbuf loads on kepler+ computeIlia Mirkin2017-02-091-25/+22
* nvc0: increase number of ubo binding pointsIlia Mirkin2017-02-091-3/+2
* nvc0: expose int64Ilia Mirkin2017-02-091-1/+1
* nvc0/ir: make it possible to have the flags def in def0Ilia Mirkin2017-02-095-12/+15
* nvc0/ir: add support for 64-bit shift lowering on SM20/SM30Ilia Mirkin2017-02-091-6/+62
* nvc0/ir: add support for all the new int64 tgsi opcodesIlia Mirkin2017-02-096-5/+302
* nv50/ir: Split 64-bit integer MAD/MUL operationsPierre Moreau2017-02-091-0/+116
* nvc0/ir: add a "high" subop for shifts, emit shf.l/shf.r for 64-bitIlia Mirkin2017-02-093-3/+74
* nvc0/ir: fix SET and SLCT emissionIlia Mirkin2017-02-092-0/+6
* nvc0/ir: add support for emitting partial min/max ops for int64Ilia Mirkin2017-02-094-1/+14
* gallium: add separate PIPE_CAP_INT64_DIVMODIlia Mirkin2017-02-0917-0/+18
* swr: [rasterizer jitter] Pass LLVM-IR size into jitterTim Rowley2017-02-083-3/+4
* swr: [rasterizer core] Frontend SIMD16 WIPTim Rowley2017-02-084-293/+331
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