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* nir: add a bit_size parameter to nir_ssa_dest_initConnor Abbott2016-03-176-15/+15
* nir: rename nir_const_value fields to include bitsize informationIago Toral Quiroga2016-03-174-14/+14
* nir: update opcode definitions for different bit sizesConnor Abbott2016-03-171-1/+3
* vc4: Move discard handling to the condition flag.Eric Anholt2016-03-165-34/+29
* vc4: Don't make a temporary for setting flags.Eric Anholt2016-03-161-1/+2
* vc4: Add a safety check for setting flags.Eric Anholt2016-03-161-0/+3
* vc4: Reuse list_for_each_entry_safe_rev().Eric Anholt2016-03-161-6/+2
* vc4: Coalesce instructions using VPM reads into the VPM read.Varad Gautam2016-03-153-7/+71
* vc4: rename file to group vpm optimizations togetherVarad Gautam2016-03-152-2/+2
* vc4: Fix failures with nir_extract_* since the addition of the opcodes.Eric Anholt2016-03-151-0/+2
* llvmpipe: fix lp_rast_plane alignment on 32bitRoland Scheidegger2016-03-152-0/+8
* draw: fix line stipplingRoland Scheidegger2016-03-151-15/+15
* softpipe: fix misleading TGSI_QUAD_SIZE usageRoland Scheidegger2016-03-151-24/+29
* softpipe: fix anisotropic filtering crashRoland Scheidegger2016-03-151-2/+7
* radeonsi: set DEPTH_BEFORE_SHADER based on FS_EARLY_DEPTH_STENCILNicolai Hähnle2016-03-141-0/+3
* tgsi: add tgsi_full_src_register_from_dst helper functionNicolai Hähnle2016-03-142-0/+20
* gallium/u_inlines: add util_copy_image_viewNicolai Hähnle2016-03-141-0/+10
* gallium: add access field to pipe_image_viewNicolai Hähnle2016-03-142-1/+10
* tgsi: add TGSI_PROPERTY_FS_EARLY_DEPTH_STENCILNicolai Hähnle2016-03-143-1/+9
* st/glsl_to_tgsi: provide Texture and Format information for image opsNicolai Hähnle2016-03-142-5/+15
* tgsi: add Texture and Format to tgsi_instruction_memoryNicolai Hähnle2016-03-142-1/+11
* clover: Fix pipe_grid_info.indirect not being initialized.Hans de Goede2016-03-141-1/+1
* gallium/swr: Resource managementBruce Cherniak2016-03-1410-143/+265
* nv50,nvc0: Set only NEW_CP_GLOBALS upon bindingPierre Moreau2016-03-132-2/+2
* freedreno/ir3: lower extract_byte/wordRob Clark2016-03-131-0/+2
* nv50,nvc0: handle SQRT lowering inside the driverIlia Mirkin2016-03-136-23/+27
* nv50/ir: avoid folding mul + add if the mul has a dnzIlia Mirkin2016-03-131-3/+2
* nvc0: fix blit triangle size to fully cover FB's > 8192x8192Ilia Mirkin2016-03-131-4/+4
* freedreno: OUT_RELOC vs OUT_RELOCW fixesRob Clark2016-03-133-7/+7
* freedreno/a4xx: hw binningRob Clark2016-03-134-33/+210
* freedreno/a4xx: use generated headers for draw initiatorRob Clark2016-03-131-3/+4
* freedreno/a4xx: remove RB_RENDER_CONTROL patchingRob Clark2016-03-136-41/+8
* freedreno: update generated headersRob Clark2016-03-135-11/+32
* freedreno/a3xx: move where we deal w/ binning FSRob Clark2016-03-133-10/+10
* freedreno/a4xx: move where we deal w/ binning FSRob Clark2016-03-133-10/+10
* freedreno/a3xx: constify the shader variantsRob Clark2016-03-132-6/+6
* freedreno/a4xx: constify the shader variantsRob Clark2016-03-134-13/+13
* freedreno/a3xx: remove duplicate mark of end of binning cmdsRob Clark2016-03-131-3/+0
* radeonsi: avoid crash when a sampler state is bound for a buffer textureNicolai Hähnle2016-03-131-0/+1
* st/va: add HEVC main 10 profileBoyuan Zhang2016-03-111-1/+4
* radeon/video: enable HEVC main 10 decodeBoyuan Zhang2016-03-111-2/+6
* radeon/uvd: handle HEVC main 10 decodeBoyuan Zhang2016-03-111-11/+58
* radeonsi: Lazily re-set sampler views after disabling DCCBas Nieuwenhuizen2016-03-112-5/+8
* r600g: clear compressed_depthtex/colortex_mask when binding buffer textureNicolai Hähnle2016-03-111-12/+12
* nvc0: add support for TGSI FMA opsIlia Mirkin2016-03-102-1/+7
* radeonsi: update compressed_colortex_masks when a cmask is created or disabledNicolai Hähnle2016-03-103-2/+51
* radeonsi: move si_decompress_textures to si_blit.cNicolai Hähnle2016-03-103-23/+23
* r600g: update compressed_colortex_masks when a cmask is created or disabledNicolai Hähnle2016-03-101-0/+30
* gallium/radeon: notify all contexts when cmasks are enabled/disabledNicolai Hähnle2016-03-102-0/+10
* gallium/swr: remove use of BYTE from swr driverTim Rowley2016-03-104-14/+14
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