aboutsummaryrefslogtreecommitdiffstats
path: root/src/gallium/winsys
Commit message (Expand)AuthorAgeFilesLines
* winsys/svga/drm: Fix 32-bit RPCI send messageDeepak Rawat2019-06-061-12/+23
* winsys/drm: Fix out of scope variable usageDeepak Rawat2019-06-021-12/+13
* build: Build etnaviv drmGuido Günther2019-06-051-2/+4
* amd/common: use generated register headerNicolai Hähnle2019-06-032-2/+1
* radeonsi: clean up winsys creationMarek Olšák2019-05-271-8/+0
* ac: treat Mullins as Kabini, remove the enumMarek Olšák2019-05-271-3/+0
* svga: Add an environment variable to force coherent surface memoryThomas Hellstrom2019-05-174-3/+18
* pipebuffer, winsys/svga: Add functionality to update pb_validate_entry flagsThomas Hellstrom2019-05-171-16/+7
* winsys/svga: Fix RELOC_INTERNAL mob GPU accessThomas Hellstrom2019-05-171-1/+9
* svga: Remove the surface_invalidate winsys functionThomas Hellstrom2019-05-173-18/+0
* r600+radeonsi: use ctx_query_reset_status on radeonMarek Olšák2019-05-162-8/+0
* winsys/radeon: implement ctx_query_reset_status by copying radeonsiMarek Olšák2019-05-164-6/+43
* winsys/amdgpu: report a CS rejection as a reset only if there's no GPU resetMarek Olšák2019-05-161-6/+5
* winsys/amdgpu: add REWIND emulation via INDIRECT_BUFFER into cs_check_spaceMarek Olšák2019-05-162-8/+15
* winsys/amdgpu: add a parallel compute IB coupled with a gfx IBMarek Olšák2019-05-163-5/+160
* winsys/amdgpu: always set NO_CPU_ACCESS and NO_SUBALLOC on GDS resourcesMarek Olšák2019-05-161-2/+5
* ac: rename SI-CIK-VI to GFX6-GFX7-GFX8Marek Olšák2019-05-155-24/+24
* v3d: Use driconf to expose non-MSAA texture limits for Xorg.Eric Anholt2019-05-136-15/+25
* winsys/amdgpu: add VCN JPEG to no user fence groupLeo Liu2019-05-101-1/+2
* virgl: export resource_is_busy from winsysChia-I Wu2019-05-062-11/+14
* svga: move host logging to winsysCharmaine Lee2019-05-025-0/+495
* winsys/svga: Don't abort on EBUSY errors from execbufferThomas Hellstrom2019-05-021-1/+3
* winsys/svga: Update the drm interface fileThomas Hellstrom2019-05-022-174/+188
* winsys/svga: Enable the transfer_from_buffer GPU command for vgpu10Thomas Hellstrom2019-05-021-0/+1
* winsys/svga: Add an environment variable to force host-backed operationThomas Hellstrom2019-05-021-6/+11
* winsys/svga/drm: Include sys/types.hKhem Raj2019-04-301-0/+1
* vc4: Fall back to renderonly if the vc4 driver doesn't have v3d.Eric Anholt2019-04-262-3/+35
* kmsro: Add support for V3D.Eric Anholt2019-04-262-0/+16
* virgl/drm: insert correct handles into the table. (v3)Dave Airlie2019-04-251-1/+4
* virgl/drm: handle flink name better.Dave Airlie2019-04-252-20/+11
* virgl/drm: cleanup buffer from handle creation (v2)Dave Airlie2019-04-252-15/+13
* winsys/amdgpu: clean up and remove nonsensical assertionMarek Olšák2019-04-231-2/+1
* winsys/amdgpu: enable chaining for compute IBsMarek Olšák2019-04-231-6/+6
* winsys/amdgpu: reorder chunks, make BO_HANDLES first, IB and FENCE lastMarek Olšák2019-04-231-19/+17
* winsys/amdgpu: make IBs writable and expose their addressMarek Olšák2019-04-231-1/+3
* ac: add radeon_info::marketing_name, replacing the winsys callbackMarek Olšák2019-04-231-7/+0
* iris: Add mechanism for iris-specific driconf optionsKenneth Graunke2019-04-222-3/+5
* lima: add Android buildIcenowy Zheng2019-04-211-0/+32
* virgl/vtest: bump up protocol version + support encoded transfersGurchetan Singh2019-04-183-3/+12
* virgl/vtest: wait after issuing a transfer getGurchetan Singh2019-04-181-2/+3
* virgl/vtest: modify sending and receiving data for shared memoryGurchetan Singh2019-04-181-4/+35
* virgl/vtest: receive and handle shared memory fdGurchetan Singh2019-04-182-7/+55
* virgl/vtest: plumb support for shared memoryGurchetan Singh2019-04-183-6/+10
* virgl/vtest: add utilities for receiving fdsGurchetan Singh2019-04-181-0/+43
* virgl/vtest: execute a transfer_get when flushing the front bufferGurchetan Singh2019-04-181-22/+21
* winsys/amdgpu: don't set GTT with GDS & OA placements on APUsMarek Olšák2019-04-161-9/+11
* virgl: fix fence fd version checkChia-I Wu2019-04-151-2/+2
* virgl: introduce virgl_drm_fenceChia-I Wu2019-04-152-45/+115
* virgl: hide fence internals from the driverChia-I Wu2019-04-152-28/+42
* virgl: handle fence_server_sync in winsysChia-I Wu2019-04-153-12/+25
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-09 08:29:29 +0000