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* freedreno/ir3: remove pipe_stream_output_info dependencyRob Clark2018-11-278-17/+68
* freedreno/ir3: some header file cleanupRob Clark2018-11-2711-26/+24
* freedreno/ir3: use env_var_as_unsigned()Rob Clark2018-11-272-14/+2
* freedreno/ir3: move disasm and optmsgs debug flagsRob Clark2018-11-279-22/+25
* freedreno: FD_SHADER_DEBUG -> IR3_SHADER_DEBUGRob Clark2018-11-274-33/+34
* freedreno: remove shader_stage_name()Rob Clark2018-11-273-21/+3
* freedreno: shader_t -> gl_shader_stageRob Clark2018-11-2722-143/+121
* freedreno/ir3: standalone compiler updatesRob Clark2018-11-271-6/+27
* freedreno: move drm to common locationRob Clark2018-11-2720-3717/+12
* freedreno/drm: remove dependency on gallium driverRob Clark2018-11-271-2/+11
* nv50/ir: remove dnz flag when converting MAD to ADD due to optimizationsIlia Mirkin2018-11-241-0/+3
* virgl: add assert and missing function parameterRobert Foss2018-11-211-1/+4
* r600: clean up the GS ring buffers when the context is destroyedGert Wollny2018-11-211-0/+6
* radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSEDMarek Olšák2018-11-201-11/+4
* radeonsi: don't send data after write-confirm with BOTTOM_OF_PIPE_TSMarek Olšák2018-11-203-9/+5
* meson: Add tests to suitesDylan Baker2018-11-202-2/+4
* nir: Make nir_lower_clip_vs optionally work with variables.Kenneth Graunke2018-11-192-2/+3
* etnaviv: use dummy RT buffer when rendering without color bufferLucas Stach2018-11-193-2/+19
* radeonsi: fix an out-of-bounds read reported by ASANNicolai Hähnle2018-11-191-0/+4
* r600: Only set context streamout strides info from the shader that has outputsGert Wollny2018-11-191-3/+9
* virgl: Clean up fences commitRobert Foss2018-11-181-1/+1
* nv50/ir/ra: enforce max register requirement, and change spill orderIlia Mirkin2018-11-164-16/+26
* nv50/ir/ra: improve condition for short regs, unify with cond for 16-bitIlia Mirkin2018-11-161-7/+7
* nv50/ir: delete MINMAX instruction that is no longer in the BBIlia Mirkin2018-11-161-1/+1
* virgl: native fence fd supportRobert Foss2018-11-163-10/+62
* vc4: Don't return a vc4 BO handle on a renderonly screen.Eric Anholt2018-11-151-2/+4
* vc4: Make sure we make ro scanout resources for create_with_modifiers.Eric Anholt2018-11-151-1/+9
* v3d: Fix double-swapping of R/B on V3D 4.1Eric Anholt2018-11-151-2/+3
* etnaviv: Make sure rs alignment checks matchGuido Günther2018-11-151-6/+13
* radeonsi: fix video APIs on Raven2Marek Olšák2018-11-142-4/+8
* virgl: Add command and flags to initiate debugging on the host (v2)Gert Wollny2018-11-135-0/+37
* freedreno/drm: fix unused 'entry' warningsRob Clark2018-11-121-2/+0
* radeonsi: stop command submission with PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET onlyMarek Olšák2018-11-0912-17/+20
* radeonsi: don't set the CB clear color registers for 0/1 clear colors on Raven2Marek Olšák2018-11-094-3/+11
* radeonsi: use better DCC clear codesMarek Olšák2018-11-091-5/+21
* gm107/ir: fix compile time warning in getTEXSMaskKarol Herbst2018-11-071-0/+1
* gm107/ir: use scalar tex instructions where possibleKarol Herbst2018-11-062-3/+317
* nv50/ir: add scalar field to TexInstructionsKarol Herbst2018-11-062-1/+6
* nv50/ra: add condenseDef overloads for partial condensesKarol Herbst2018-11-061-8/+21
* nv50/ir: print color masks of tex instructionsKarol Herbst2018-11-061-4/+33
* r600: Add support for EXT_texture_sRGB_R8Gert Wollny2018-11-061-0/+1
* freedreno/a6xx: Clear z32 and separate stencil with blitterKristian H. Kristensen2018-11-062-27/+50
* freedreno/a6xx: fix VSC bug with larger # of tilesRob Clark2018-11-061-5/+2
* freedreno: update generated headersRob Clark2018-11-067-29/+51
* r600/sb: Fix constant logical operand in assert.Vinson Lee2018-11-041-1/+1
* vc4: Use the normal simulator ioctl path for CL submit as well.Eric Anholt2018-11-023-13/+5
* vc4: Maintain a separate GEM mapping of BOs in the simulator.Eric Anholt2018-11-022-42/+58
* vc4: Take advantage of _mesa_hash_table_remove_key() in the simulator.Eric Anholt2018-11-021-4/+2
* v3d: Remove the special path for simulaton of the submit ioctl.Eric Anholt2018-11-025-19/+13
* v3d: Maintain a mapping of the GEM buffer in the simulator.Eric Anholt2018-11-021-23/+48
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