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* broadcom/vc5: Fix image_h setup for both loads and stores.Eric Anholt2018-02-011-3/+2
| | | | | | | The image_h for the tiling algorithm needs to be the padded-to-a-uifblock height of the level, not the unpadded height or the height of level 0. Fixes some cases of KHR-GLES3.texture_repeat_mode.* and depthstencil-render-miplevels.
* broadcom/vc5: Add appropriate height padding for bank conflicts.Eric Anholt2018-02-014-0/+63
| | | | | | | I thought I didn't need this because I was doing level-0-always-UIF and that the pad there would propagate down, but it turns out that for level 1 the padding ends up being chosen by the HW. This brings us closer to being able to turn on UIF XOR for increased performance, as well.
* broadcom/vc5: Simplify separate stencil surface setup.Eric Anholt2018-02-013-99/+77
| | | | | | | | | If we just make another gallium surface for the separate stencil, it's a lot easier to keep track of which set of fields we're using in RCL setup. This also incidentally fixes a little bug in setting up the surface's padded height for separate stencil when the UIF-ness changes at different levels of Z versus stencil.
* broadcom/vc5: Rename the UIFCFG register in the UAPI.Eric Anholt2018-02-012-2/+2
| | | | | | This matches the naming of the other hub regs we get, and I don't know for sure if UIFCFG will be the same register between the hub and the cores on all versions.
* broadcom/vc5: Skip over missing color buffers for a couple of checks.Eric Anholt2018-02-012-0/+6
| | | | Fixes crashes in piglit alpha-to-coverage-no-draw-buffer-zero 2
* broadcom/vc5: Add the missing PIPE_CAP_FENCE_SIGNAL.Eric Anholt2018-02-011-0/+1
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* radeonsi: use ac_build_buffer_load_format for image buffer loadsMarek Olšák2018-02-011-4/+10
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: add glc parameter to ac_build_buffer_load_formatMarek Olšák2018-02-012-2/+2
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: load the right number of components for VS inputs and TBOsMarek Olšák2018-02-012-5/+16
| | | | | | | | | | | | | | | | | | | | | | | The supported counts are 1, 2, 4. (3=4) The following snippet loads float, vec2, vec3, and vec4: Before: buffer_load_format_x v9, v4, s[0:3], 0 idxen ; E0002000 80000904 buffer_load_format_xyzw v[0:3], v5, s[8:11], 0 idxen ; E00C2000 80020005 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_load_format_xyzw v[2:5], v6, s[12:15], 0 idxen ; E00C2000 80030206 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_load_format_xyzw v[5:8], v7, s[4:7], 0 idxen ; E00C2000 80010507 After: buffer_load_format_x v10, v4, s[0:3], 0 idxen ; E0002000 80000A04 buffer_load_format_xy v[8:9], v5, s[8:11], 0 idxen ; E0042000 80020805 buffer_load_format_xyzw v[0:3], v6, s[12:15], 0 idxen ; E00C2000 80030006 s_waitcnt vmcnt(0) ; BF8C0F70 buffer_load_format_xyzw v[3:6], v7, s[4:7], 0 idxen ; E00C2000 80010307 Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: remove unused si_shader_context membersMarek Olšák2018-02-012-11/+0
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* r600/eg: make sure we allow vpm bit on other CF ops.Dave Airlie2018-02-011-0/+1
| | | | | | | the vpm bit wasn't being applied to the push/pop instructions. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/sb: just add some missing debug bitsDave Airlie2018-02-011-0/+15
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600: fix buffer resinfo opcode translation.Dave Airlie2018-02-012-2/+2
| | | | | | | | | The vtx operations never got translated, so things worked by 0 being equal to 0, translate them so we can use the proper buffer resinfo code. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* svga: use opcode local var to simplify some codeBrian Paul2018-01-311-4/+2
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* svga: s/unsigned/VGPU10_OPCODE_TYPE/Brian Paul2018-01-311-10/+11
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* virgl: also remove dimension on indirect.Dave Airlie2018-01-311-1/+0
| | | | | | | | | This fixes some dEQP tests that generated bad shaders. Fixes: b6f6ead19 (virgl: drop const dimensions on first block.) Reviewed-by: Gurchetan Singh <[email protected]> Tested-by: Gurchetan Singh <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: remove DBG_PRECOMPILEMarek Olšák2018-01-313-51/+0
| | | | | | it's useless and shader-db stats only report the main shader part. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: print shader-db stats for main parts, not final binariesMarek Olšák2018-01-313-13/+23
| | | | | | This is needed to get shader-db stats for LS,HS,ES,GS stages on gfx9. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move max_simd_waves computation into a separate functionMarek Olšák2018-01-312-12/+23
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* nir: add lower_all_io_to_temps flagTimothy Arceri2018-01-312-0/+2
| | | | | | | This will be used for freedreno and vc4 which require all inputs and outputs to be copied to temps. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: add input support for arrays that have not been copied to ↵Timothy Arceri2018-01-311-67/+79
| | | | | | | | | temps and split We need this to be able to support the interpolateAt builtins in a sane way. It also leads to the generation of more optimal code. Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add lookup_interp_param and load_sample_position to the abiTimothy Arceri2018-01-311-0/+2
| | | | | | | This will enable the interpolateAt builtins to work on the radeonsi nir backend. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: add prim_mask to the abiTimothy Arceri2018-01-311-3/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: adjust load_sample_position() to be shared between backendsTimothy Arceri2018-01-311-2/+3
| | | | | | | With this interface change it can be shared between the tgsi and nir backends. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: add si_nir_lookup_interp_param() helperTimothy Arceri2018-01-312-0/+40
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: move the interpolation qualifier scanningTimothy Arceri2018-01-311-16/+36
| | | | | | | | We need to collect this when scanning over the instruction rather than when scanning over the inputs otherwise we might get confliting values for inputs that are use by the interpolateAt* builtins. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: add interpolate at intrinsics to scan_instruction()Timothy Arceri2018-01-311-0/+30
| | | | | | V2: use the uses_*_opcode_interp_* flags Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix fence_server_sync() holding up extra work v2Andres Rodriguez2018-01-302-25/+28
| | | | | | | | | | | | | | | When calling si_fence_server_sync(), the wait operation is associated with the next kernel submission. Therefore, any unflushed work submitted previous to fence_server_sync() will also be affected by the wait. To avoid adding the dependency to the unflushed work, we flush before emitting the fence dependency. v2: s/semaphore/fence Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement semaphore_server_signal v2Andres Rodriguez2018-01-301-0/+37
| | | | | | | | | | | Syncobj based waits or signals only happen at submission boundaries. In order to guarantee that the requested signal event will occur when the state tracker requested it, we must issue a flush. v2: s/fence/semaphore for pipe objects Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add support for importing PIPE_FD_TYPE_SYNCOBJ semaphoresAndres Rodriguez2018-01-301-6/+20
| | | | | | | Hook up importing semaphores of type PIPE_FD_TYPE_SYNCOBJ Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* winsys/amdgpu: add support for syncobj signaling v3Andres Rodriguez2018-01-301-0/+12
| | | | | | | | | | Add the ability to signal a syncobj when a cs completes execution. v2: corresponding changes for gallium fence->semaphore rename v3: s/semaphore/fence for pipe objects Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: introduce PIPE_CAP_FENCE_SIGNAL v2Andres Rodriguez2018-01-3016-1/+15
| | | | | | | | | Protects semaphore signaling functionality required by GL_EXT_semaphore. v2: s/semaphore/fence Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add type parameter to create_fence_fdAndres Rodriguez2018-01-306-6/+17
| | | | | | | | | | | An fd can potentially have different types of objects backing it. Specifying the type helps us make sure we treat the FD correctly. This is in preparation to allow importing syncobj fence FDs in addition to native sync FDs. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600/sb: insert the else clause when we might depart from a loopDave Airlie2018-01-311-0/+17
| | | | | | | | | | | | | | If there is a break inside the else clause and this means we are breaking from a loop, the loop finalise will want to insert the LOOP_BREAK/CONTINUE instruction, however if we don't emit the else there is no where for these to end up, so they will end up in the wrong place. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101442 Tested-By: Gert Wollny <[email protected]> Cc: <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* svga: Check rasterization state object before checking poly_stipple_enableNeha Bhende2018-01-291-1/+1
| | | | | | | | | | | | | | Sometimes rasterization state object could be empty. This is causing segfault on hw8,9,10 for some traces. This patch fixes enemy_territory_quake_wars_high, enemy_territory_quake_wars_low, etqw-demo, lightsmark2008, quake1 glretrace crashes on hw 8,9,10. Tested with mtt-glretrace and mtt-piglit. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: Adjust alpha for S3TC_DXT1_EXT RGB formatsNeha Bhende2018-01-291-0/+4
| | | | | | | | | | | | According to spec, S3TC_DXT1_EXT RGB formats are supposed to be opaque. Correspoding svga formats are not handling it so explicitly setting it to 1.0. This fixes piglit test spec@ext_texture_compression_s3tc@s3tc-targeted Note: This test is testcase for freedesktop bug 100925 Tested with mtt-piglit and mtt-glretrace on 8,9,10,11 and 15 Reviewed-by: Brian Paul <[email protected]>
* radeonsi/nir: add support vs double inputsTimothy Arceri2018-01-301-0/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: pass input_idx to declare_nir_input_vs()Timothy Arceri2018-01-301-2/+3
| | | | | | | This make it consistent with declare_nir_input_fs() and will allow us to support doubles. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add bitcast_inputs() helperTimothy Arceri2018-01-301-6/+15
| | | | | | Will be used in a following patch to help support doubles. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: fix num_inputs for doubles in vsTimothy Arceri2018-01-301-5/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600: add ARB_query_buffer_object supportDave Airlie2018-01-2910-31/+817
| | | | | | | | | | | | | | This uses a different shader than radeonsi, as we can't address non-256 aligned ssbos, which the radeonsi code does. This passes some extra offsets into the shader. It also contains a set of u64 instruction implementation that may or may not be complete (at least the u64div is definitely not something that works outside this use-case). If r600 grows 64-bit integers, it will use the GLSL lowering for divmod. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: refactor mul hi/lo instruction emissionDave Airlie2018-01-291-254/+116
| | | | | | | This just makes it a bit simpler for cayman vs eg Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/eg: construct proper rat mask for image/buffers.Dave Airlie2018-01-293-8/+30
| | | | | | | | | | If the images/buffer bindings had a gap, this produced the wrong values, this should fix that to generate the correct rat mask for mixes of images/buffers/cbs. Reviewed-by: Roland Scheidegger <[email protected]> Cc: "18.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* broadcom/vc5: Don't forget to get the BO offset when opening a dmabuf.Eric Anholt2018-01-271-0/+12
| | | | Fixes black display in DRI due to storing to 0x00000000.
* broadcom/vc5: Enable the driver on V3D 4.2.Eric Anholt2018-01-271-1/+6
| | | | | | The changes in 4.2 haven't impacted any of our CL or state struct entries that I can see, so I haven't enabled custom compile for doing 4.2 instead of 4.1.
* ac: rename and move si_const_array into common codeMarek Olšák2018-01-273-18/+9
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: move address space definitions to common codeMarek Olšák2018-01-271-8/+3
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: don't use byval LLVM qualifier in shadersMarek Olšák2018-01-271-12/+5
| | | | | | | shader-db doesn't show any regression and 32-bit pointers with byval are declared as VGPRs for some reason. Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/radeon: set number of pb_cache buckets = number of heapsMarek Olšák2018-01-271-20/+0
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/radeon: simplify radeon_flags_from_heapMarek Olšák2018-01-271-14/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
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