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* swr: Limit DEBUG workaround to LLVM < 7Michel Dänzer2019-09-173-3/+21
* etnaviv: a bit of micro-optimizationChristian Gmeiner2019-09-172-1/+4
* lima: reset scissor state if scissor test is disabledIcenowy Zheng2019-09-171-0/+4
* lima: add standalone disassembler with primitive MBS parserVasily Khoruzhick2019-09-162-0/+219
* radeonsi/nir: fix number of used samplersTimothy Arceri2019-09-161-1/+1
* iris: Fix fence leak in iris_fence_flushDanylo Piliaiev2019-09-161-0/+2
* iris: Initialize ice->state.prim_mode to an invalid valueKenneth Graunke2019-09-131-0/+1
* lima/ppir: Add undef handlingAndreas Baierl2019-09-134-4/+24
* lima/ppir: Rename ppir_op_dummy to ppir_op_undefAndreas Baierl2019-09-133-5/+5
* panfrost: Move the batch submission logic to panfrost_batch_submit()Boris Brezillon2019-09-135-172/+127
* panfrost: Move the fence creation in panfrost_flush()Boris Brezillon2019-09-134-15/+15
* panfrost: Delay payloads[].offset_start initializationBoris Brezillon2019-09-131-3/+3
* panfrost: Prepare things to avoid flushes on FB switchBoris Brezillon2019-09-132-8/+12
* panfrost: Pass a batch to panfrost_set_value_job()Boris Brezillon2019-09-131-4/+2
* panfrost: Use ctx->wallpaper_batch in panfrost_blit_wallpaper()Boris Brezillon2019-09-131-4/+5
* panfrost: Pass a batch to functions emitting FB descsBoris Brezillon2019-09-136-53/+44
* panfrost: Pass a batch to panfrost_{allocate,upload}_transient()Boris Brezillon2019-09-1310-41/+57
* panfrost: Allow testing if a specific batch is targeting a scanout FBBoris Brezillon2019-09-135-24/+23
* panfrost: Get rid of the unused 'flush jobs accessing res' infraBoris Brezillon2019-09-133-49/+0
* panfrost: Use a pipe_framebuffer_state as the batch keyBoris Brezillon2019-09-132-38/+17
* radeon/vcn: exclude raven2 from vcn 2.0 encode initializationIndrajit Das2019-09-131-1/+1
* v3d: fix TF primitive counts for resume without drawIago Toral Quiroga2019-09-133-1/+17
* v3d: remove redundant update of queued draw callsIago Toral Quiroga2019-09-131-2/+0
* v3d: make sure we have enough space in the CL for the primitive counts packetIago Toral Quiroga2019-09-131-0/+1
* v3d: add missing line break for performance debug messageIago Toral Quiroga2019-09-131-1/+1
* panfrost/ci: Use releases for Volt dEQPTomeu Vizoso2019-09-132-4/+6
* panfrost/ci: Update kernel to 5.3-rc8Tomeu Vizoso2019-09-132-2/+2
* panfrost/ci: Run dEQP with the surfaceless platformTomeu Vizoso2019-09-134-24/+44
* freedreno/a6xx: pre-calculate userconst stateobj sizeRob Clark2019-09-124-3/+44
* freedreno: fix compiler warningRob Clark2019-09-121-1/+1
* meson/v3d: replace partial list of nir dep files with idep_nir_headersEric Engestrom2019-09-121-2/+2
* meson/iris: replace partial list of nir dep files with idep_nir_headersEric Engestrom2019-09-121-3/+2
* v3d: flag dirty state when binding compute statesJose Maria Casanova Crespo2019-09-124-38/+47
* iris: trivial whitespace fixesKenneth Graunke2019-09-111-2/+2
* intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WMAnuj Phogat2019-09-111-0/+9
* gallium: Require LLVM >= 3.4Adam Jackson2019-09-111-4/+0
* meson: don't generate file into subdirsDylan Baker2019-09-111-1/+1
* iris: Set bo->reusable = false in iris_bo_make_external_lockedKenneth Graunke2019-09-111-5/+4
* iris: Finish initializing the BO before stuffing it in the hash tableKenneth Graunke2019-09-111-4/+2
* radeonsi/gfx9: honor user stride for imported buffersMarek Olšák2019-09-111-0/+2
* lima: set .out_sync field of req in lima_submit_start()Vasily Khoruzhick2019-09-101-0/+1
* freedreno/a6xx: fix 3d tex layoutRob Clark2019-09-101-3/+4
* freedreno/a6xx: don't tile things that are too smallRob Clark2019-09-102-5/+11
* iris: Enable ARB_gl_spirv and ARB_spirv_extensionsCaio Marcelo de Oliveira Filho2019-09-101-0/+2
* iris: Fix constant buffer sizes for non-UBOsKenneth Graunke2019-09-101-3/+4
* radeonsi: remove redundant si_texture offset and size fieldsMarek Olšák2019-09-097-123/+106
* radeonsi: move texture storage allocation outside of radeonsiMarek Olšák2019-09-091-48/+10
* radeonsi: move HTILE allocation outside of radeonsiMarek Olšák2019-09-091-88/+12
* radeonsi: handle NO_DCC earlyMarek Olšák2019-09-091-5/+7
* ac/surface: add RADEON_SURF_NO_FMASKMarek Olšák2019-09-091-6/+3
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