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src
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gallium
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drivers
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virgl
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Author
Age
Files
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...
*
virgl: add VIRGL_DEBUG_SYNC
Chia-I Wu
2019-06-25
3
-1
/
+20
*
virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLE
Chia-I Wu
2019-06-25
2
-8
/
+10
*
android: virgl: fix libmesa_winsys_virgil_common build and dependencies
Mauro Rossi
2019-06-21
1
-1
/
+1
*
virgl: Add debug flag to bypass driconf to enable the BGRA tweaks
Gert Wollny
2019-06-20
2
-0
/
+8
*
virgl: Add a tweak to set the value for emulated queries of GL_SAMPLES_PASSED
Gert Wollny
2019-06-20
5
-1
/
+12
*
virgl: Add tweak to apply a swizzle when drawing/blitting to a emulated BGRA ...
Gert Wollny
2019-06-20
5
-0
/
+9
*
virgl: Add driconf tweak for emulating BGRA surfaces on GLES
Gert Wollny
2019-06-20
3
-0
/
+10
*
virgl: Add override for BGRA format to use swizzled SRGB format
Gert Wollny
2019-06-20
4
-1
/
+27
*
virgl: Add code to accept BGRx_SRGB as RGBx_SRGB
Gert Wollny
2019-06-20
2
-3
/
+23
*
virgl: Add skeleton to evaluate cap and send tweaks
Gert Wollny
2019-06-20
5
-0
/
+31
*
virgl: factor out format host bits check
Gert Wollny
2019-06-20
1
-16
/
+17
*
gallium/virgl: Add code path for virgl to read driconf
Gert Wollny
2019-06-20
2
-2
/
+3
*
virgl: Add driinfo file and tie it into the build
Gert Wollny
2019-06-20
3
-2
/
+36
*
virgl: Support VIRGL_BIND_SHARED
David Riley
2019-06-19
2
-0
/
+3
*
virgl: fix sync issue regarding discard/unsync transfers
Chia-I Wu
2019-06-18
1
-5
/
+15
*
virgl_hw: add YUV support
Gurchetan Singh
2019-06-18
1
-0
/
+6
*
virgl: sync to virglrenderer virgl_hw.h
Gurchetan Singh
2019-06-18
1
-3
/
+10
*
virgl: Assume sRGB write control for older guest kernels or virglrenderer hosts
Gert Wollny
2019-06-17
1
-1
/
+2
*
virgl: better support for PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
Chia-I Wu
2019-06-17
4
-25
/
+92
*
virgl: add virgl_rebind_resource
Chia-I Wu
2019-06-17
4
-0
/
+148
*
virgl: save virgl_hw_res in virgl_transfer
Chia-I Wu
2019-06-17
5
-14
/
+22
*
virgl: add resource_reference to virgl_winsys
Chia-I Wu
2019-06-17
2
-2
/
+4
*
virgl: virgl_transfer should own its virgl_resource
Chia-I Wu
2019-06-12
2
-8
/
+6
*
virgl: pass virgl_context to transfer create/destroy
Chia-I Wu
2019-06-12
5
-22
/
+21
*
virgl: init transfer queue from virgl_context
Chia-I Wu
2019-06-12
3
-10
/
+11
*
virgl: clean up virgl_transfer_queue.h
Chia-I Wu
2019-06-12
2
-1
/
+13
*
virgl: Work around possible memory exhaustion
Alexandros Frantzis
2019-06-07
3
-3
/
+22
*
virgl: Remove incorrect resource wait condition
Alexandros Frantzis
2019-06-07
1
-13
/
+0
*
virgl: Use copy transfers for textures
Alexandros Frantzis
2019-06-07
2
-9
/
+87
*
virgl: Use buffer copy transfers to avoid waiting when mapping
Alexandros Frantzis
2019-06-07
6
-6
/
+137
*
virgl: Support copy transfers
Alexandros Frantzis
2019-06-07
5
-5
/
+70
*
virgl: Add copy_transfer3d definitions
Alexandros Frantzis
2019-06-07
2
-0
/
+9
*
virgl: Support VIRGL_BIND_STAGING
Alexandros Frantzis
2019-06-07
3
-4
/
+16
*
virgl: Avoid unfinished transfer_get with PIPE_TRANSFER_DONTBLOCK
Alexandros Frantzis
2019-06-07
1
-9
/
+12
*
virgl: More info about chosen alignment value
Alexandros Frantzis
2019-06-07
1
-0
/
+5
*
virgl: store all info about atomic buffers
Chia-I Wu
2019-06-07
2
-16
/
+23
*
virgl: add shader images to virgl_shader_binding_state
Chia-I Wu
2019-06-07
2
-14
/
+27
*
virgl: add SSBOs to virgl_shader_binding_state
Chia-I Wu
2019-06-07
2
-14
/
+26
*
virgl: add UBOs to virgl_shader_binding_state
Chia-I Wu
2019-06-07
2
-20
/
+37
*
virgl: add virgl_shader_binding_state
Chia-I Wu
2019-06-07
2
-43
/
+44
*
virgl: Enable CAP_CLIP_HALFZ if host supports it
Gert Wollny
2019-06-06
2
-1
/
+3
*
virgl: resolve to correct level during texture read
Chia-I Wu
2019-06-04
1
-2
/
+2
*
virgl: fix texture resolving with compressed formats
Chia-I Wu
2019-06-04
1
-12
/
+17
*
virgl: fix readback with pending transfers
Chia-I Wu
2019-05-29
1
-6
/
+26
*
virgl: remove an incorrect check in virgl_res_needs_flush
Chia-I Wu
2019-05-24
1
-15
/
+0
*
virgl: reemit resources on first draw/clear/compute
Chia-I Wu
2019-05-24
1
-6
/
+24
*
virgl: add missing emit_res for SO targets
Chia-I Wu
2019-05-24
1
-2
/
+8
*
gallium: Change PIPE_CAP_TGSI_FS_FBFETCH bool to PIPE_CAP_FBFETCH count
Kenneth Graunke
2019-05-23
1
-2
/
+3
*
virgl: track valid buffer range for transfer sync
Chia-I Wu
2019-05-22
7
-20
/
+59
*
virgl: remove support for buffer surfaces
Chia-I Wu
2019-05-22
2
-19
/
+15
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