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path: root/src/gallium/drivers/virgl/virgl_context.c
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* virgl: Encode barrier for blend_equation_advancedElie Tournier2020-07-171-1/+2
* virgl: implement ARB_clear_textureElie Tournier2020-05-071-0/+19
* gallium: add pipe cap for scissored clears and pass scissor state to clear() ...Mike Blumenkrantz2020-04-291-0/+1
* util: Move gallium's PIPE_FORMAT utils to /util/format/Eric Anholt2019-11-141-1/+1
* gallium: add PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE to skip util_range lockMarek Olšák2019-10-071-1/+1
* virgl: Enable depth_clamp by lowering if the host is new enough.Gert Wollny2019-08-011-0/+3
* tree-wide: replace MAYBE_UNUSED with ASSERTEDEric Engestrom2019-07-311-1/+1
* virgl: Use virgl_staging_mgrAlexandros Frantzis2019-06-281-11/+7
* virgl: add VIRGL_DEBUG_SYNCChia-I Wu2019-06-251-1/+18
* virgl: Add a tweak to set the value for emulated queries of GL_SAMPLES_PASSEDGert Wollny2019-06-201-0/+4
* virgl: Add tweak to apply a swizzle when drawing/blitting to a emulated BGRA ...Gert Wollny2019-06-201-0/+3
* virgl: Add driconf tweak for emulating BGRA surfaces on GLESGert Wollny2019-06-201-0/+2
* virgl: Add skeleton to evaluate cap and send tweaksGert Wollny2019-06-201-0/+7
* virgl: add virgl_rebind_resourceChia-I Wu2019-06-171-0/+130
* virgl: init transfer queue from virgl_contextChia-I Wu2019-06-121-1/+1
* virgl: Work around possible memory exhaustionAlexandros Frantzis2019-06-071-0/+5
* virgl: Use buffer copy transfers to avoid waiting when mappingAlexandros Frantzis2019-06-071-0/+15
* virgl: store all info about atomic buffersChia-I Wu2019-06-071-14/+21
* virgl: add shader images to virgl_shader_binding_stateChia-I Wu2019-06-071-13/+24
* virgl: add SSBOs to virgl_shader_binding_stateChia-I Wu2019-06-071-13/+23
* virgl: add UBOs to virgl_shader_binding_stateChia-I Wu2019-06-071-18/+34
* virgl: add virgl_shader_binding_stateChia-I Wu2019-06-071-37/+37
* virgl: reemit resources on first draw/clear/computeChia-I Wu2019-05-241-6/+24
* virgl: track valid buffer range for transfer syncChia-I Wu2019-05-221-0/+3
* virgl: remove support for buffer surfacesChia-I Wu2019-05-221-12/+11
* virgl: remove unused virgl_transfer_inline_writeChia-I Wu2019-05-141-33/+0
* virgl: skip empty cmdbufsChia-I Wu2019-04-231-0/+8
* virgl: clear vertex_array_dirtyChia-I Wu2019-04-221-0/+2
* virgl: wait after a flushGurchetan Singh2019-04-181-1/+4
* virgl: remove pointless transfer-counterErik Faye-Lund2019-04-171-1/+1
* virgl: hide fence internals from the driverChia-I Wu2019-04-151-11/+1
* virgl: handle fence_server_sync in winsysChia-I Wu2019-04-151-5/+1
* gallium: add writable_bitmask parameter into set_shader_buffersMarek Olšák2019-04-041-1/+2
* virgl: use uint16_t mask instead of separate booleansGurchetan Singh2019-03-131-5/+1
* virgl: remove unused variableErik Faye-Lund2019-03-071-1/+0
* virgl: use transfer queueGurchetan Singh2019-02-151-0/+13
* virgl: make winsys modifications for encoded transfersGurchetan Singh2019-02-151-1/+1
* virgl: pass virgl transfer to virgl_res_needs_flush_waitGurchetan Singh2019-02-151-1/+10
* virgl: keep track of number of computationsGurchetan Singh2019-02-151-1/+2
* virgl: unmap uploader at flush timeGurchetan Singh2019-02-151-2/+3
* virgl: make alignment smaller when uploading index user buffersGurchetan Singh2019-02-151-1/+1
* virgl: track level cleanliness rather than resource cleanlinessGurchetan Singh2019-02-151-4/+8
* virgl: use virgl_resource_dirty helperGurchetan Singh2019-02-151-4/+4
* virgl: add ability to do finer grain dirty trackingGurchetan Singh2019-02-151-4/+4
* virgl: Set sRGB write control CAP based on host capabilitiesGert Wollny2019-01-281-0/+10
* virgl: use primconvert provoking vertex properlyDave Airlie2019-01-081-8/+18
* virgl: move resource metadata into base resourceGurchetan Singh2018-12-191-3/+2
* virgl: modify how we handle GL_MAP_FLUSH_EXPLICIT_BITGurchetan Singh2018-12-191-33/+1
* virgl: texture_transfer_pool --> transfer_poolGurchetan Singh2018-12-191-2/+2
* virgl: work around bad assumptions in virglrendererErik Faye-Lund2018-12-131-1/+32
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