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path:
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src
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gallium
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drivers
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vc4
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vc4_qir_schedule.c
Commit message (
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Author
Age
Files
Lines
*
vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.
Eric Anholt
2016-11-29
1
-23
/
+27
*
vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).
Eric Anholt
2016-11-29
1
-4
/
+4
*
vc4: Make sure we don't overflow texture input/output FIFOs when threaded.
Eric Anholt
2016-11-22
1
-2
/
+3
*
vc4: Add THRSW nodes after each tex sample setup in multithreaded mode.
Eric Anholt
2016-11-12
1
-0
/
+24
*
vc4: Add some spec citations about texture fifo management.
Eric Anholt
2016-11-12
1
-5
/
+37
*
vc4: Emit resets of the uniform stream at the starts of blocks.
Eric Anholt
2016-07-13
1
-0
/
+16
*
vc4: Define a QIR branch instruction
Eric Anholt
2016-07-12
1
-0
/
+8
*
vc4: Make vc4_qir_schedule handle each block in the program.
Eric Anholt
2016-07-12
1
-14
/
+23
*
vc4: Create a basic block structure and move the instructions into it.
Eric Anholt
2016-07-12
1
-2
/
+3
*
Remove wrongly repeated words in comments
Giuseppe Bilotta
2016-06-23
1
-1
/
+1
*
vc4: Fix doxygen warnings
12.0-branchpoint
Rhys Kidd
2016-05-30
1
-2
/
+2
*
vc4: Allow TLB Z/color/stencil writes from any ALU operation in QIR.
Eric Anholt
2016-04-08
1
-11
/
+24
*
vc4: Add missing scheduling dependency for MS color writes.
Eric Anholt
2016-04-08
1
-0
/
+1
*
vc4: Move discard handling to the condition flag.
Eric Anholt
2016-03-16
1
-5
/
+0
*
vc4: Add missing braces in initializer
Rhys Kidd
2016-02-15
1
-1
/
+1
*
vc4: Replace the SSA-style SEL operators with conditional MOVs.
Eric Anholt
2016-01-06
1
-4
/
+3
*
vc4: Do instruction scheduling on the QIR to hide texture fetch latency.
Eric Anholt
2015-12-18
1
-0
/
+619