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path: root/src/gallium/drivers/vc4/vc4_qir_schedule.c
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* vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.Eric Anholt2016-11-291-23/+27
* vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).Eric Anholt2016-11-291-4/+4
* vc4: Make sure we don't overflow texture input/output FIFOs when threaded.Eric Anholt2016-11-221-2/+3
* vc4: Add THRSW nodes after each tex sample setup in multithreaded mode.Eric Anholt2016-11-121-0/+24
* vc4: Add some spec citations about texture fifo management.Eric Anholt2016-11-121-5/+37
* vc4: Emit resets of the uniform stream at the starts of blocks.Eric Anholt2016-07-131-0/+16
* vc4: Define a QIR branch instructionEric Anholt2016-07-121-0/+8
* vc4: Make vc4_qir_schedule handle each block in the program.Eric Anholt2016-07-121-14/+23
* vc4: Create a basic block structure and move the instructions into it.Eric Anholt2016-07-121-2/+3
* Remove wrongly repeated words in commentsGiuseppe Bilotta2016-06-231-1/+1
* vc4: Fix doxygen warnings12.0-branchpointRhys Kidd2016-05-301-2/+2
* vc4: Allow TLB Z/color/stencil writes from any ALU operation in QIR.Eric Anholt2016-04-081-11/+24
* vc4: Add missing scheduling dependency for MS color writes.Eric Anholt2016-04-081-0/+1
* vc4: Move discard handling to the condition flag.Eric Anholt2016-03-161-5/+0
* vc4: Add missing braces in initializerRhys Kidd2016-02-151-1/+1
* vc4: Replace the SSA-style SEL operators with conditional MOVs.Eric Anholt2016-01-061-4/+3
* vc4: Do instruction scheduling on the QIR to hide texture fetch latency.Eric Anholt2015-12-181-0/+619