aboutsummaryrefslogtreecommitdiffstats
path: root/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
Commit message (Expand)AuthorAgeFilesLines
* swr/rast: Enable generalized fetch jitGeorge Kyriazis2018-04-181-1022/+115
* swr/rast: Add builder_gfx_mem.{h|cpp}George Kyriazis2018-04-181-4/+3
* swr/rast: Lower PERMD and PERMPS to x86.George Kyriazis2018-04-181-10/+10
* swr/rast: Start refactoring of builder/packetizer.George Kyriazis2018-04-181-0/+3
* swr/rast: Code cleanupGeorge Kyriazis2018-04-181-8/+1
* swr/rast: Add autogen of helper llvm intrinsics.George Kyriazis2018-04-181-5/+3
* swr/rast: Silence some unused variable warningsGeorge Kyriazis2018-04-181-1/+11
* swr/rast: Introduce JIT_MEM_CLIENTGeorge Kyriazis2018-04-181-3/+3
* swr/rast: Refactor memory gather operationsGeorge Kyriazis2018-03-091-5/+2
* swr/rast: Consolidate TRANSLATE_ADDRESSGeorge Kyriazis2018-02-281-4/+0
* swr/rast: whitespace changeGeorge Kyriazis2018-02-281-1/+1
* swr/rast: Add semantics for translating addressGeorge Kyriazis2018-02-161-0/+4
* swr/rast: Renamed variable in vertexbufferstateGeorge Kyriazis2018-02-161-4/+6
* swr/rast: Cleanup of mpPrivateContext in BuilderGeorge Kyriazis2018-02-161-2/+3
* swr/rast: Don't include private context in gather argsGeorge Kyriazis2018-02-161-2/+1
* swr/rast: Add extra (optional) parameter in GATHERPSGeorge Kyriazis2018-01-251-3/+6
* swr/rast: jit shader lib debug workGeorge Kyriazis2018-01-191-0/+6
* swr/rast: Shorten some filenamesGeorge Kyriazis2018-01-191-1/+1
* swr/rast: Debug Symbols workGeorge Kyriazis2018-01-191-0/+2
* swr/rast: Add private state parameter in fetcherGeorge Kyriazis2018-01-191-15/+24
* swr/rast: don't use 32-bit gathers for elements < 32-bits in sizeTim Rowley2018-01-101-1/+60
* swr/rast: SIMD16 fetch shader jitter cleanupTim Rowley2018-01-101-720/+368
* swr/rast: shuffle header files for msvc pre-compiled header usageTim Rowley2018-01-101-2/+1
* swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)Tim Rowley2018-01-101-77/+91
* swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffleTim Rowley2017-12-151-16/+14
* swr/rast: Replace VPSRL with LSHRTim Rowley2017-12-151-4/+4
* swr/rast: Remove no-op VBROADCAST of vIDTim Rowley2017-12-151-2/+2
* swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex componentsTim Rowley2017-12-151-17/+69
* swr/rast: Replace INSERT2 vextract/vinsert with JOIN2 vshuffleTim Rowley2017-12-151-70/+22
* swr/rast: SIMD16 Fetch - Fully widen 16-bit float vertex componentsTim Rowley2017-12-151-7/+48
* swr/rast: SIMD16 Fetch - Fully widen 32-bit float vertex componentsTim Rowley2017-12-151-26/+149
* swr/rast: Rewrite Shuffle8bpcGatherd using shuffleTim Rowley2017-12-151-182/+62
* swr/rast: Convert gather masks to Nx1bitTim Rowley2017-12-151-27/+7
* swr/rast: WIP - Widen fetch shader to SIMD16Tim Rowley2017-12-151-27/+689
* swr/rast: Remove unneeded copy of gather maskTim Rowley2017-12-151-60/+20
* swr/rast: Implement AVX-512 GATHERPS in SIMD16 fetch shaderTim Rowley2017-11-201-14/+77
* swr/rast: Simplify GATHER* jit builder apiTim Rowley2017-11-201-28/+28
* swr/rast: Widen fetch shader to SIMD16Tim Rowley2017-11-201-3/+54
* swr/rast: Widen fetch shader to SIMD16 (disabled for now)Tim Rowley2017-10-191-13/+428
* swr/rast: Handle instanceID offset / Instance Stride enableTim Rowley2017-09-251-7/+39
* swr/rast: Fetch compile state changesTim Rowley2017-09-251-0/+6
* swr/rast: Fetch compile state changesTim Rowley2017-09-131-2/+10
* swr/rast: Allow gather of floats from fetch shader with 2-4GB offsetsTim Rowley2017-09-061-1/+6
* swr/rast: SIMD16 shaders - widen fetch and vertex shadersTim Rowley2017-08-021-5/+170
* swr/rast: remove unused variablesTim Rowley2017-07-061-2/+0
* swr/rast: Implement JIT shader caching to diskTim Rowley2017-06-161-2/+4
* swr/rast: use gather instruction for odd format fetchTim Rowley2017-04-281-46/+9
* swr: [rasterizer jitter] fix llvm >= 5.0 build breakTim Rowley2017-03-221-1/+1
* swr: [rasterizer] Cleanup naming of codegen filesTim Rowley2017-03-201-1/+1
* swr: [rasterizer] Convert more SWR_ASSERT(false, ...) to SWR_INVALID(...)Tim Rowley2017-03-201-7/+7