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* radeonsi: use a threaded context even for debug contextsNicolai Hähnle2017-11-091-9/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: record and dump time of flushNicolai Hähnle2017-11-093-1/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement PIPE_FLUSH_{TOP,BOTTOM}_OF_PIPENicolai Hähnle2017-11-091-1/+88
| | | | | | | v2: use uncached system memory for the fence, and use the CPU to clear it so we never read garbage when checking the fence Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: document some subtle details of fence_finish & fence_server_syncNicolai Hähnle2017-11-091-0/+22
| | | | | | | v2: remove the change to si_fence_server_sync, we'll handle that more robustly Reviewed-by: Marek Olšák <[email protected]>
* gallium/u_threaded: implement asynchronous flushesNicolai Hähnle2017-11-093-25/+84
| | | | | | | | | | | | | This requires out-of-band creation of fences, and will be signaled to the pipe_context::flush implementation by a special TC_FLUSH_ASYNC flag. v2: - remove an incorrect assertion - handle fence_server_sync for unsubmitted fences by relying on the improved cs_add_fence_dependency - only implement asynchronous flushes on amdgpu Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move fence functions to si_fence.cNicolai Hähnle2017-11-095-0/+312
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: always use async compiles when creating shader/compute statesNicolai Hähnle2017-11-092-34/+50
| | | | | | | | | | | | | | With Gallium threaded contexts, creating shader/compute states is effectively a screen operation, so we should not use context state. In particular, this allows us to avoid using the context's LLVM TargetMachine. This isn't an issue yet because u_threaded_context filters out non-async debug callbacks, and we disable threaded contexts for debug contexts. However, we may want to change that in the future. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix potential use-after-free of debug callbacksNicolai Hähnle2017-11-091-0/+4
| | | | | | Found by inspection. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: move pipe debug callback to si_contextNicolai Hähnle2017-11-094-6/+19
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: reduce the scope of sel->mutex in si_shader_select_with_keyNicolai Hähnle2017-11-091-4/+4
| | | | | | | | | | We only need the lock to guard changes in the variant linked list. The actual compilation can happen outside the lock, since we use the ready fence as a guard. v2: fix double-unlock Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use ready fences on all shaders, not just optimized onesNicolai Hähnle2017-11-093-26/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a race condition between si_shader_select_with_key and si_bind_XX_shader: Thread 1 Thread 2 -------- -------- si_shader_select_with_key begin compiling the first variant (guarded by sel->mutex) si_bind_XX_shader select first_variant by default as state->current si_shader_select_with_key match state->current and early-out Since thread 2 never takes sel->mutex, it may go on rendering without a PM4 for that shader, for example. The solution taken by this patch is to broaden the scope of shader->optimized_ready to a fence shader->ready that applies to all shaders. This does not hurt the fast path (if anything it makes it faster, because we don't explicitly check is_optimized). It will also allow reducing the scope of sel->mutex locks, but this is deferred to a later commit for better bisectability. Fixes dEQP-EGL.functional.sharing.gles2.multithread.simple.buffers.bufferdata_render Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add si_screen::has_ls_vgpr_init_bugMarek Olšák2017-11-074-3/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ac_create_target_machineMarek Olšák2017-11-071-15/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ac_get_llvm_processor_nameMarek Olšák2017-11-071-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't set gs_table_depthMarek Olšák2017-11-071-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven onlyMarek Olšák2017-11-071-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable signed vertex buffer offsetsMarek Olšák2017-11-062-15/+12
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* gallium: add PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSETMarek Olšák2017-11-061-0/+1
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* ac/radeonsi: add support for tex instr without a derefenceTimothy Arceri2017-11-031-0/+5
| | | | | | | | | | | These are produced by nir_lower_bitmap(), adding the missing derefence would cause other issues that need to be hacked around such as skipping sampler lowering and uniform location assignment, so this change seems the correct way to go. Fixes 194 piglit crashes on radeonsi using NIR. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove 'Authors:' commentsMarek Olšák2017-11-0219-66/+0
| | | | | | | It's inaccurate. Instead, see the copyright and use "git log" and "git blame" to know the authorship. Acked-by: Nicolai Hähnle <[email protected]>
* gallium: add cap for driver specified max combined shader resources.Dave Airlie2017-11-011-0/+1
| | | | | | | | Some hw (evergreen) has a limit on how many combined (images/buffers/mrts) a fragment shader can access. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: fix culldist_writemask in nir pathTimothy Arceri2017-11-011-2/+1
| | | | | | | | | | | | The shared si_create_shader_selector() code already offsets the mask. Fixes the following piglit tests: arb_cull_distance/clip-cull-3.shader_test arb_cull_distance/clip-cull-4.shader_test Fixes: 29d7bdd179bb (radeonsi: scan NIR shaders to obtain required info) Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: update hack for HTILE corruption in ARK: Survival EvolvedSamuel Pitoiset2017-10-274-9/+9
| | | | | | | | | | | | It appears that flushing the DB metadata is actually not sufficient since the driver uses the new VS blit shaders. This looks quite strange though, but it seems like we need to flush DB for fixing the corruption. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955 Fixes: 69ccb9dae7 (radeonsi: use new VS blit shaders (VS inputs in SGPRs) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add a workaround for weird s_buffer_load_dword behavior on SIMarek Olšák2017-10-261-3/+10
| | | | | | | | | | | | | | See my LLVM patch which fixes the root cause. Users have to apply this patch and then they have 2 choices: - Downgrade to LLVM 5.0 - Update to LLVM git after my LLVM patch is pushed. It won't be possible to use current and earlier development version of LLVM 6.0. Reviewed-by: Nicolai Hähnle <[email protected]> Cc: 17.3 <[email protected]>
* ac/llvm: consolidate find lsb function.Dave Airlie2017-10-261-25/+2
| | | | | | | This was the same between si and ac. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/nir: move lds declaration/load/store into shared code.Dave Airlie2017-10-262-16/+5
| | | | | | | This was duplicated between both drivers, share here. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: postponed KILL isn't postponed anymore, but maintains WQMMarek Olšák2017-10-241-0/+6
| | | | | | | | | | | | | This restores performance for the drirc workaround, i.e. KILL_IF does: visible = src0 >= 0; kill_flag &= visible; // accumulate kills amdgcn_kill(wqm_vote(visible)); // kill fully dead quads only And all helper pixels are killed at the end of the shader: amdgcn_kill(kill_flag); Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use postponed KILL only when derivatives are usedMarek Olšák2017-10-244-3/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: replace ac_build_kill with ac_build_kill_if_falseMarek Olšák2017-10-242-52/+38
| | | | | | | This will be a new LLVM intrinsic and will also work nicely with llvm.amdgcn.wqm.vote. Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/nir: Only clamp shadow reference on radeonsi.Bas Nieuwenhuizen2017-10-231-0/+1
| | | | | | | | | | | | | | | | | | Vulkan CTS does not expect the value to be clamped (at least for D32), and it makes a differences even though depth is in [0,1], due to strict inequalities. I couldn't find anything in the Vulkan spec about this, but the test seemed to be copied from GL tests and the GL spec only specifies clamping for fixed point formats. Hence I expect radeonsi to run into this at some point as well, but given that they still have a usecase with the Z16->Z32 promotion, I'll leave that for someone else to clean up. This at least fixes radv dEQP-VK.texture.shadow.* on VI. Fixes: 0f9e32519bb 'ac/nir: clamp shadow texture comparison value on VI' Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: hardcode shader WAVE_LIMIT to the maximum valueAndres Rodriguez2017-10-211-7/+14
| | | | | | | | | | | | | This is part of a cooperative scheduling approach used by radv. All drivers in the stack must opt-in to resource arbitration, otherwise GL based apps will be able to ignore system priorities. We always hardcode the field to its maximum value, instead of attempting to calculate an approximate usage. In testing, there were no benefits to using anything other than the maximum. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: Get rid of nir_shader::stageJason Ekstrand2017-10-201-11/+11
| | | | | | | | It's redundant with nir_shader::info::stage. Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* radeonsi: if there's just const buffer 0, set it in place of CONST/SSBO pointerMarek Olšák2017-10-174-13/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SI_SGPR_CONST_AND_SHADER_BUFFERS now contains the pointer to const buffer 0 if there is no other buffer there. Benefits: - there is no constbuf descriptor upload and shader load It's assumed that all constant addresses are within bounds. Non-constant addresses are clamped against the last declared CONST variable. This only works if the state tracker ensures the bound constant buffer matches what the shader needs. Once we get 32-bit pointers, we can only do this for user constant buffers where the driver is in charge of the upload so that it can guarantee a 32-bit address. The real performance benefit might not be measurable. These apps get 100% theoretical benefit in all shaders (except where noted): - antichamber - barman arkham origins - borderlands 2 - borderlands pre-sequel - brutal legend - civilization BE - CS:GO - deadcore - dota 2 -- most shaders - europa universalis - grid autosport -- most shaders - left 4 dead 2 - legend of grimrock - life is strange - payday 2 - portal - rocket league - serious sam 3 bfe - talos principle - team fortress 2 - thea - unigine heaven - unigine valley -- also sanctuary and tropics - wasteland 2 - xcom: enemy unknown & enemy within - tesseract - unity (engine) Changed stats only: SGPRS: 2059998 -> 2086238 (1.27 %) VGPRS: 1626888 -> 1626904 (0.00 %) Spilled SGPRs: 7902 -> 7865 (-0.47 %) Code Size: 60924520 -> 60982660 (0.10 %) bytes Max Waves: 374539 -> 374526 (-0.00 %) Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: clean up ac_build_indexed_load function interfacesMarek Olšák2017-10-172-19/+19
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: handle 64-bit loads earlier in fetch_constantMarek Olšák2017-10-171-16/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add si_descriptors::gpu_address and remove buffer_offsetMarek Olšák2017-10-173-14/+18
| | | | | | This allows us to change the pointer arbitrarily. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: unify code for extracting a buffer address from a descriptorMarek Olšák2017-10-171-4/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove atom parameter from si_upload_descriptorsMarek Olšák2017-10-171-8/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: pack si_descriptors better againMarek Olšák2017-10-171-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: emit dirty consecutive pointers in one SET_SH_REG packetMarek Olšák2017-10-171-27/+39
| | | | | | IB size: -1.6% Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: split si_emit_shader_pointerMarek Olšák2017-10-171-11/+23
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: generalize the SI_VS_SHADER_POINTER_MASK macroMarek Olšák2017-10-173-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: use SPI_SHADER_USER_DATA_COMMONMarek Olšák2017-10-171-13/+13
| | | | | | IB size: -0.4% Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: move RW_BUFFERS from s[0:1] to s[8:9] for HS and GSMarek Olšák2017-10-172-39/+16
| | | | | | | Let's use the same user data SGPRs in all stages. (for SPI_SHADER_USER_DATA_COMMON_0) Reviewed-by: Nicolai Hähnle <[email protected]>
* meson: build radeonsi gallium driverDylan Baker2017-10-161-1/+1
| | | | | | | | | | This hooks up the bits necessary to build gallium dri drivers, with radeonSI as the first example driver. This isn't tested yet. v4: - drop radeonsi generated header from sources. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: build radeonsiDylan Baker2017-10-161-0/+78
| | | | | | | | This builds the radeonsi (and radeon) window system bits and gallium driver bits. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* radeonsi: implement sync_file import/exportMarek Olšák2017-10-121-1/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORMNicolai Hähnle2017-10-121-0/+8
| | | | | | Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: lower ffma in nir to mad.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | This lowers ffma to a * b + c. This seems like it should keep Marek happiest, so we'd never get to the fma instruction emission code. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.Eric Anholt2017-10-101-0/+1
| | | | | | | | | | | | | | | | Because vc4 can control the order that tiles are rasterized in, we can use it to implement overlapping blits using normal drawing and GL_ARB_texture_barrier, as long as we can tell the kernel what order to render the tiles in. This commit introduces the core gallium support, vc4 changes will follow. v2: Fix on the simulator. v3: Add the cap (disabled) to other drivers, add rst docs for the cap. v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS v5: Drop vc4 changes from this commit, for clarity. Reviewed-by: Nicolai Hähnle <[email protected]> (v3)
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