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path: root/src/gallium/drivers/radeonsi/si_state_draw.c
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* radeonsi: rename tcs_tes_uses_prim_id for clarityNicolai Hähnle2017-05-161-2/+2
* gallium: remove pipe_index_buffer and set_index_bufferMarek Olšák2017-05-101-45/+46
* gallium: separate indirect stuff from pipe_draw_info - 80 -> 56 bytesMarek Olšák2017-05-101-27/+32
* radeonsi: clarify documentation of existing SI workaroundNicolai Hähnle2017-05-081-1/+3
* radeonsi: fix gl_PrimitiveID in tessellation with instanced draws on SINicolai Hähnle2017-05-081-0/+14
* radeonsi: apply the tess+GS hang workaround to Polaris12 as wellMarek Olšák2017-05-051-1/+2
* radeonsi: add a HUD query for draw calls with primitive restartMarek Olšák2017-04-281-0/+2
* radeonsi: fix tess offchip offset for per-patch attributesMarek Olšák2017-04-281-2/+3
* radeonsi: pass tessellation ring addresses via user SGPRsMarek Olšák2017-04-281-1/+2
* radeonsi/gfx9: set registers and shader key for merged ES-GSMarek Olšák2017-04-281-1/+2
* radeonsi/gfx9: define and set LS-HS user SGPRsMarek Olšák2017-04-281-2/+10
* radeonsi/gfx9: set up shader registers for merged LS-HSMarek Olšák2017-04-281-7/+24
* radeonsi: code shuffling in si_emit_derived_tess_stateMarek Olšák2017-04-281-31/+38
* radeonsi/gfx9: don't set deprecated field PARTIAL_ES_WAVE_ONMarek Olšák2017-04-261-2/+3
* radeonsi/gfx9: set MAX_PRIMGRP_IN_WAVE in the correct registerMarek Olšák2017-04-261-1/+2
* radeonsi: don't allow user indices with indirect drawsMarek Olšák2017-04-171-4/+4
* radeonsi: merge two if (indirect) statementsMarek Olšák2017-04-171-27/+25
* radeonsi: fix gl_BaseVertex in non-indexed drawsNicolai Hähnle2017-04-131-2/+6
* radeonsi: provide VS_STATE input to all VS variantsNicolai Hähnle2017-04-131-4/+5
* radeonsi: change the bit-packing of LS out/TCS in dataNicolai Hähnle2017-04-131-2/+2
* radeonsi: emit VS_STATE register explicitly from si_draw_vboNicolai Hähnle2017-04-131-0/+14
* radeonsi: extract derived tess state emit to higher levelNicolai Hähnle2017-04-131-6/+7
* r600g/radeonsi: use the correct types (taken from pipe_draw_info)Constantine Kharlamov2017-04-041-2/+3
* radeonsi: don't make a copy of pipe_index_buffer in draw_vboMarek Olšák2017-03-301-32/+27
* radeonsi/gfx9: flush CB & DB caches with an EOP TS eventMarek Olšák2017-03-301-23/+84
* radeonsi/gfx9: use ACQUIRE_MEMMarek Olšák2017-03-301-6/+17
* radeonsi/gfx9: draw changesMarek Olšák2017-03-301-12/+31
* radeonsi/gfx9: add a scissor bug workaroundMarek Olšák2017-03-301-0/+6
* radeonsi: handle MultiDrawIndirect in si_get_draw_start_countNicolai Hähnle2017-02-211-7/+53
* gallium/u_index_modify: don't add PIPE_TRANSFER_UNSYNCHRONIZED unconditionallyMarek Olšák2017-02-191-1/+1
* radeonsi: fix UNSIGNED_BYTE index buffer fallback with non-zero start (v2)Marek Olšák2017-02-191-2/+2
* radeonsi: use a clever alignment for index buffer uploadsMarek Olšák2017-02-181-4/+7
* radeonsi: move index buffer flushing into a non-upload indexed caseMarek Olšák2017-02-181-7/+6
* gallium/radeon: remove the internal u_upload_mgr pointerMarek Olšák2017-02-141-2/+4
* radeonsi: remove SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFERMarek Olšák2017-02-101-1/+2
* radeonsi: remove separate CB/DB_META flush flagsMarek Olšák2017-02-101-10/+5
* gallium/radeon: merge dirty_fb_counter and dirty_tex_descriptor_counterMarek Olšák2017-01-301-11/+5
* radeonsi: handle count_from_stream_output in a few IA_MULTI_VGT_PARAM casesMarek Olšák2017-01-301-2/+4
* radeonsi: fold info->indirect conditionals into the last one in draw_vboMarek Olšák2017-01-301-12/+13
* radeonsi: atomize the scratch buffer stateMarek Olšák2017-01-301-24/+0
* radeonsi: precompute IA_MULTI_VGT_PARAM values into a tableMarek Olšák2017-01-301-72/+120
* radeonsi: move VGT_VERTEX_REUSE_BLOCK_CNTL into shader states for PolarisMarek Olšák2017-01-301-19/+0
* radeonsi: use a bitmask for looping over dirty PM4 statesMarek Olšák2017-01-301-2/+15
* radeonsi: atomize L2 prefetchesMarek Olšák2017-01-301-36/+1
* radeonsi: update dirty_level_mask only after the first draw after FB changeMarek Olšák2017-01-301-24/+28
* radeonsi: always set the TCL1_ACTION_ENA when invalidating L2Marek Olšák2017-01-231-1/+2
* radeonsi: use a global dirty mask for shader pointersMarek Olšák2017-01-181-1/+1
* ac/debug: Move IB decode to common code.Bas Nieuwenhuizen2017-01-091-1/+3
* radeonsi: add TC L2 prefetch for shaders and VBO descriptorsMarek Olšák2017-01-061-1/+36
* radeonsi: add HUD queries for cache flush statsMarek Olšák2017-01-061-0/+5
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