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path: root/src/gallium/drivers/radeonsi/si_pipe.c
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* radeonsi: rename r600_transfer -> si_transferMarek Olšák2018-06-251-1/+1
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: clean up some #includesMarek Olšák2018-06-251-1/+1
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: add a debug flag to zero vram allocationsGrazvydas Ignotas2018-06-211-0/+1
| | | | | | | | | | This allows to avoid having to see garbage in Dying Light loading screen at least, which probably expects Windows/NV behavior of all allocations being zeroed by default. Analogous to radv flag with the same name. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: rename r600_texture -> si_texture, rxxx -> xxx or sxxxMarek Olšák2018-06-191-1/+1
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbufMarek Olšák2018-06-191-1/+1
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* amd: remove support for LLVM 4.0Marek Olšák2018-05-171-1/+1
| | | | | | | It doesn't support GFX9. Acked-by: Dave Airlie <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* ac/gpu_info: add has_eqaa_surface_allocatorMarek Olšák2018-05-101-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up the reset status query implementationMarek Olšák2018-05-101-20/+16
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add an environment variable that forces EQAA for MSAA allocationsMarek Olšák2018-05-101-0/+25
| | | | | | This is for testing and experiments. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: increase the number of compiler threads depending on the CPUMarek Olšák2018-04-271-13/+26
| | | | | | | | | The compiler queue was limited to 3 threads, so shader-db running on a 16-thread CPU would have a bottleneck on the 3-thread queue. Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: avoid a crash in gallivm_dispose_target_library_infoMarek Olšák2018-04-271-0/+3
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move data_layout into si_compilerMarek Olšák2018-04-271-0/+9
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move passmgr into si_compilerMarek Olšák2018-04-271-0/+30
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move target_library_info into si_compilerMarek Olšák2018-04-271-0/+10
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add triple into si_compilerMarek Olšák2018-04-271-1/+2
| | | | | | Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add struct si_compiler containing LLVMTargetMachineRefMarek Olšák2018-04-271-24/+28
| | | | | | | | It will contain more variables. Reviewed-by: Timothy Arceri <[email protected]> Tested-by: Benedikt Schemmer <ben at besd.de> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use r600_resource() typecast helperMarek Olšák2018-04-271-9/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: inline 2 trivial state structuresMarek Olšák2018-04-271-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_pipe_common.hMarek Olšák2018-04-271-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fully enable 2x DCC MSAA for array and non-array texturesMarek Olšák2018-04-271-4/+1
| | | | | | | The clear code is exactly the same as for 1 sample buffers - just clear the whole thing. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use common gs_table_depth codeDave Airlie2018-04-241-31/+2
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: don't runtime check gs table infoDave Airlie2018-04-241-7/+7
| | | | | | | | We can just unreachable here, this aligns with radv code, makes it easier to move to common code. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: add support for VegaMMarek Olšák2018-04-181-0/+1
| | | | Acked-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix a hang with an empty first IBMarek Olšák2018-04-181-3/+4
| | | | | | | | This packet causes the no-op IB detection to fail, so the IB is always submitted. Also fix the no-op IB detection by moving the begin call. Cc: 18.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: move ddebug, noop, rbug, trace to auxiliary to improve build timesMarek Olšák2018-04-131-1/+1
| | | | which also simplifies the build scripts.
* radeonsi: remove r600_common_contextMarek Olšák2018-04-051-102/+102
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::screenMarek Olšák2018-04-051-1/+0
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: rename a few R600/r600_ -> SI_/si_Marek Olšák2018-04-051-1/+1
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: move definitions out of r600_pipe_common.hMarek Olšák2018-04-051-4/+4
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: move functions out of and remove r600_pipe_common.cMarek Olšák2018-04-051-2/+145
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: use si_context instead of pipe_context in parameters pt2Marek Olšák2018-04-051-2/+2
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: use r600_common_context less pt6Marek Olšák2018-04-051-2/+2
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: update copyrightsMarek Olšák2018-04-051-0/+2
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: use r600_common_context less pt2Marek Olšák2018-04-051-1/+1
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: flatten / remove struct r600_ringMarek Olšák2018-04-051-2/+2
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_ring::flush callbackMarek Olšák2018-04-051-1/+0
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: rename si_begin_new_cs -> si_begin_new_gfx_csMarek Olšák2018-04-051-1/+1
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: remove r600_pipe_common::set_atom_dirtyMarek Olšák2018-04-051-1/+0
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: call CS flush functions directly whenever possibleMarek Olšák2018-04-051-2/+2
| | | | Acked-by: Timothy Arceri <[email protected]>
* radeonsi: add R600_DEBUG=nofmask to disable MSAA compressionMarek Olšák2018-04-021-0/+1
| | | | | | For testing. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: use maximum OFFCHIP_BUFFERING on Vega12Marek Olšák2018-03-281-1/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: add support for Vega12Marek Olšák2018-03-281-0/+2
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: put both tessellation rings into 1 bufferMarek Olšák2018-02-241-2/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move tessellation ring info into si_screenMarek Olšák2018-02-241-2/+36
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix regression from 32-bit pointers on CIMarek Olšák2018-02-191-1/+1
| | | | Tested-by: Michel Dänzer <[email protected]>
* radeonsi: implement 32-bit pointers in user data SGPRs (v2)Marek Olšák2018-02-171-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | User SGPRs changes: VS: 14 -> 9 TCS: 14 -> 10 TES: 10 -> 6 GS: 8 -> 4 GSCOPY: 2 -> 1 PS: 9 -> 5 Merged VS-TCS: 24 -> 16 Merged VS-GS: 18 -> 11 Merged TES-GS: 18 -> 11 SGPRS: 2170102 -> 2158430 (-0.54 %) VGPRS: 1645656 -> 1641516 (-0.25 %) Spilled SGPRs: 9078 -> 8810 (-2.95 %) Spilled VGPRs: 130 -> 114 (-12.31 %) Scratch size: 1508 -> 1492 (-1.06 %) dwords per thread Code Size: 52094872 -> 52692540 (1.15 %) bytes Max Waves: 371848 -> 372723 (0.24 %) v2: - the shader cache needs to take address32_hi into account - set amdgpu-32bit-address-high-bits Reviewed-by: Samuel Pitoiset <[email protected]> (v1)
* gallium: use PIPE_CAP_CONSTBUF0_FLAGSMarek Olšák2018-02-171-1/+1
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* st/radeonsi: enable disk cache for nirTimothy Arceri2018-02-101-4/+0
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: copy the NIR enablement debug bit to the shader cache flagsMarek Olšák2018-02-091-1/+2
| | | | | | | When NIR is enabled, TGSI must not be used. When NIR is disabled, TGSI Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: remove DBG_PRECOMPILEMarek Olšák2018-01-311-1/+0
| | | | | | it's useless and shader-db stats only report the main shader part. Reviewed-by: Nicolai Hähnle <[email protected]>
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