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path: root/src/gallium/drivers/radeonsi/si_hw_context.c
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* r600: fork and import gallium/radeonMarek Olšák2017-09-261-5/+5
* radeonsi/gfx9: implement primitive binningMarek Olšák2017-09-051-0/+2
* radeonsi: remove Constant Engine supportMarek Olšák2017-08-221-49/+2
* radeonsi: print saved CS to the log contextNicolai Hähnle2017-08-221-21/+46
* radeonsi: don't prefetch VBO descriptors if vertex elements == NULLMarek Olšák2017-08-211-1/+1
* radeonsi: don't use CLEAR_STATE on SIMarek Olšák2017-08-181-7/+13
* radeonsi: add a separate dirty mask for prefetchesMarek Olšák2017-08-071-2/+14
* radeonsi: de-atomize L2 prefetchMarek Olšák2017-08-071-1/+1
* radeonsi: print CE IBs into ddebug reportsMarek Olšák2017-08-011-4/+6
* radeonsi: rely on CLEAR_STATE for clearing UCP and blend color registersMarek Olšák2017-07-281-2/+6
* radeonsi: rely on CLEAR_STATE for resetting the framebuffer and sample maskMarek Olšák2017-07-281-3/+10
* Revert "radeonsi: don't emit partial flushes at the end of IBs (v2)"Marek Olšák2017-06-231-9/+5
* radeonsi: don't emit partial flushes at the end of IBs (v2)Marek Olšák2017-06-221-5/+9
* radeonsi: add all resident buffers to the current CSSamuel Pitoiset2017-06-141-0/+1
* radeonsi: update si_ce_needed_cs_spaceMarek Olšák2017-05-181-8/+8
* radeonsi: do only 1 big CE dump at end of IBs and one reload in the preambleMarek Olšák2017-05-181-2/+6
* gallium/radeon: always flush asynchronously and wait after begin_new_csMarek Olšák2017-04-171-0/+3
* radeonsi: emit VS_STATE register explicitly from si_draw_vboNicolai Hähnle2017-04-131-0/+1
* radeonsi: atomize the scratch buffer stateMarek Olšák2017-01-301-1/+6
* radeonsi: move VGT_VERTEX_REUSE_BLOCK_CNTL into shader states for PolarisMarek Olšák2017-01-301-1/+0
* radeonsi: atomize L2 prefetchesMarek Olšák2017-01-301-0/+3
* radeonsi: turn SDMA IBs into de-facto preambles of GFX IBsMarek Olšák2017-01-051-4/+16
* gallium/radeon: stop using PIPE_BIND_CUSTOMMarek Olšák2016-10-261-1/+1
* gallium/radeon: implement set_device_reset_callbackNicolai Hähnle2016-10-051-0/+3
* radeonsi: move VGT_LS_HS_CONFIG to derived tess_stateMarek Olšák2016-10-041-1/+0
* radeonsi: remove the cache_flush atomMarek Olšák2016-09-091-1/+1
* radeonsi: skip redundant INDEX_TYPE writesMarek Olšák2016-09-071-0/+1
* gallium/radeon: set VPORT_ZMIN/MAX registers correctlyMarek Olšák2016-09-051-0/+1
* gallium/radeon: unify and simplify checking for an empty gfx IBMarek Olšák2016-08-251-10/+3
* gallium/radeon: count gfx IB flushesMarek Olšák2016-08-061-1/+1
* gallium/radeon: move radeon_winsys::cs_memory_below_limit to driversMarek Olšák2016-08-061-2/+3
* gallium/radeon: move last_gfx_fence from radeonsi to common codeMarek Olšák2016-08-031-5/+5
* gallium/radeon: remove RADEON_FLUSH_KEEP_TILING_FLAGS flagMarek Olšák2016-07-191-3/+0
* radeonsi: explicitly choose center locations for 1xAA on PolarisNicolai Hähnle2016-07-081-1/+2
* radeonsi: fix fractional odd tessellation spacing for PolarisMarek Olšák2016-06-241-0/+1
* radeon: check VM faults from DMA flushNicolai Hähnle2016-06-241-1/+1
* radeonsi: move gfx fence wait out of si_check_vm_faultsNicolai Hähnle2016-06-241-1/+7
* radeonsi: extract IB and bo list saving into separate functionsNicolai Hähnle2016-06-241-23/+2
* radeonsi: Reinitialize all descriptors in CE preamble.Bas Nieuwenhuizen2016-06-101-0/+3
* radeon/winsys: introduce radeon_winsys_cs_chunkNicolai Hähnle2016-06-011-4/+11
* gallium/radeon: use cs_check_space throughoutNicolai Hähnle2016-06-011-3/+2
* radeonsi: don't flush TC at the end of IBs on DRM >= 3.2.0Marek Olšák2016-05-311-2/+3
* gallium/radeon: add radeon_emitted to check for non-trivial IBsNicolai Hähnle2016-05-171-2/+2
* radeonsi: remove flushes at the beginning and end of IBs done by the kernelMarek Olšák2016-04-281-12/+12
* radeonsi: add RW_BUFFERS only once in si_ce_needed_cs_spaceMarek Olšák2016-04-261-2/+2
* radeonsi: Enable loading into CE RAM.Bas Nieuwenhuizen2016-04-211-0/+5
* radeonsi: do not do two full flushes on every compute dispatchBas Nieuwenhuizen2016-04-191-0/+1
* radeonsi: do per cs setup for compute shaders once per csBas Nieuwenhuizen2016-04-191-0/+2
* radeonsi: Create CE IB.Bas Nieuwenhuizen2016-04-191-1/+34
* radeonsi: fix a critical SI hang since PIPELINESTAT_START/STOP was addedMarek Olšák2016-04-131-1/+2
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