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radeon
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Author
Age
Files
Lines
...
*
radeon/llvm: Handle loads from the constants address space.
Tom Stellard
2012-09-21
2
-0
/
+10
*
radeon/llvm: Add support for v4f32 stores on R600
Tom Stellard
2012-09-21
3
-9
/
+27
*
radeon/llvm: Add support for i8 reads on R600
Tom Stellard
2012-09-21
3
-0
/
+25
*
radeon/llvm: Expand vector fadd and fmul on R600
Tom Stellard
2012-09-21
1
-0
/
+3
*
radeon/llvm: Add optimization for FP_ROUND
Tom Stellard
2012-09-21
2
-0
/
+27
*
radeon/llvm: Replace AMDGPU pow intrinsic with the llvm version
Tom Stellard
2012-09-21
4
-7
/
+26
*
radeon/llvm: Emit ISA for ALU instructions in the R600 code emitter
Michal Sciubidlo
2012-09-19
5
-139
/
+238
*
radeon/llvm: Only support 512 constant registers on R600
Tom Stellard
2012-09-19
1
-1
/
+1
*
radeon/llvm: Add a fdiv pattern.
Vincent Lejeune
2012-09-18
1
-3
/
+10
*
radeon/llvm: reserve also corresponding 128bits reg
Vincent Lejeune
2012-09-18
1
-0
/
+1
*
radeon/llvm: Inital flow control support for SI
Tom Stellard
2012-09-17
7
-2
/
+168
*
radeon/llvm: Fix unused variable warning
Tom Stellard
2012-09-17
1
-1
/
+0
*
radeon/llvm: Move kernel arg lowering into R600TargetLowering class
Tom Stellard
2012-09-17
6
-470
/
+35
*
radeon/llvm: Match integer add/sub for SI.
Michel Dänzer
2012-09-17
1
-2
/
+8
*
radeon/llvm: Complete integer comparison patterns for SI.
Michel Dänzer
2012-09-17
1
-4
/
+12
*
radeon/llvm: Match AMDGPUfract on SI.
Michel Dänzer
2012-09-17
1
-1
/
+3
*
radeon/llvm: Match int_AMDGPU_floor for SI.
Michel Dänzer
2012-09-17
1
-1
/
+3
*
radeon/llvm: Match vector logical operations on SI.
Michel Dänzer
2012-09-17
1
-3
/
+9
*
radeon/llvm: Support frint on SI
Christian König
2012-09-14
1
-1
/
+3
*
radeon/llvm: Fix lowering of vbuild
Tom Stellard
2012-09-13
7
-93
/
+19
*
radeon/llvm: Support fmul on SI
Tom Stellard
2012-09-13
1
-1
/
+4
*
radeon/llvm: Fix operand order of V_CNDMASK in custom inserter
Tom Stellard
2012-09-11
1
-1
/
+1
*
radeon/llvm: Assert if we try to encode an unknown register
Tom Stellard
2012-09-11
1
-1
/
+1
*
radeon/llvm: Add register encoding for VCC
Tom Stellard
2012-09-11
1
-0
/
+1
*
radeon/llvm: Ignore special registers when calculating reg count
Tom Stellard
2012-09-11
1
-0
/
+2
*
radeonsi: Handle position input parameter for pixel shaders v2
Tom Stellard
2012-09-11
2
-0
/
+22
*
radeon/llvm: Coding style fixes
Tom Stellard
2012-09-11
4
-31
/
+31
*
radeonsi: Move interpolation mode check into the compiler
Tom Stellard
2012-09-11
1
-1
/
+12
*
radeon/llvm: Add SHADER_TYPE instruction
Tom Stellard
2012-09-11
8
-1
/
+32
*
radeon/llvm: Match fexp2 for SI.
Michel Dänzer
2012-09-07
1
-1
/
+3
*
radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.
Michel Dänzer
2012-09-06
4
-0
/
+23
*
radeon/llvm: SI shader vector instructions implicitly use the EXEC register.
Michel Dänzer
2012-09-06
1
-0
/
+4
*
radeon/llvm: Extend SI EXEC register support.
Michel Dänzer
2012-09-06
2
-2
/
+7
*
radeon/llvm: Remove R600InstrInfo.td from TD_FILES
Tom Stellard
2012-09-06
1
-1
/
+0
*
radeon/llvm: Cleanup makefile
Tom Stellard
2012-09-06
2
-13
/
+37
*
radeon/llvm: Fix operand ordering for V_CNDMASK_B32
Tom Stellard
2012-09-05
1
-3
/
+3
*
radeon/llvm: Use correct float->int conversion opcode on SI.
Tom Stellard
2012-09-05
1
-2
/
+4
*
radeon/llvm: Fix lowering of SI_V_CNDLT
Tom Stellard
2012-09-04
1
-3
/
+3
*
radeon/llvm: Fix encoding of V_CNDMASK_B32
Tom Stellard
2012-09-04
2
-4
/
+4
*
radeon/llvm: do not convert f32 operand of select_cc node
Vincent Lejeune
2012-09-04
1
-20
/
+20
*
radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)
Vincent Lejeune
2012-09-04
2
-2
/
+26
*
radeon/llvm: support setcc on f32
Vincent Lejeune
2012-09-04
1
-9
/
+27
*
radon/llvm: br_cc f32 now lowered without cast
Vincent Lejeune
2012-09-04
1
-9
/
+24
*
radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and use
Vincent Lejeune
2012-09-04
2
-4
/
+4
*
radeon/llvm: fix SelectADDR8BitOffset
Christian König
2012-09-04
1
-1
/
+1
*
radeon/llvm: Rework how immediate operands are handled with SI
Tom Stellard
2012-08-31
10
-44
/
+150
*
radeon/llvm: Fix typo in assert
Tom Stellard
2012-08-31
1
-1
/
+1
*
radeon/llvm: Fix isEG tablegen predicate
Tom Stellard
2012-08-31
1
-3
/
+5
*
radeon/llvm: Add support for RCP instruction on SI
Tom Stellard
2012-08-31
1
-1
/
+3
*
radeon/llvm: Support AMDGPUfmin DAG node on SI
Tom Stellard
2012-08-31
1
-1
/
+3
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