| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | radeon/llvm: Extend SI EXEC register support. | Michel Dänzer | 2012-09-06 | 1 | -2/+4 |
| * | radeon/llvm: Rework how immediate operands are handled with SI | Tom Stellard | 2012-08-31 | 1 | -0/+1 |
| * | radeon/llvm: Create a register class for the M0 register | Tom Stellard | 2012-08-29 | 1 | -0/+2 |
| * | radeon/llvm: Basic support for SI EXEC register. | Michel Dänzer | 2012-08-28 | 1 | -0/+7 |
| * | radeon/llvm: Fix CCReg definitions on SI | Tom Stellard | 2012-07-27 | 1 | -1/+8 |
| * | radeon/llvm: Rename namespace from AMDIL to AMDGPU | Tom Stellard | 2012-07-09 | 1 | -12/+12 |
| * | radeon/llvm: Remove unused AMDIL TableGen definitons | Tom Stellard | 2012-06-18 | 1 | -10/+3 |
| * | radeonsi: Handle TGSI CONST registers | Tom Stellard | 2012-05-29 | 1 | -2/+2 |
| * | radeon/llvm: Add some comments | Tom Stellard | 2012-05-10 | 1 | -5/+6 |
| * | radeonsi: initial WIP SI code | Tom Stellard | 2012-04-13 | 1 | -0/+278 |
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