| Commit message (Expand) | Author | Age | Files | Lines |
* | radeon/llvm: Remove backend code from Mesa | Tom Stellard | 2013-01-04 | 1 | -1458/+0 |
* | radeon/llvm: use floor intrinsic instead of llvm.AMDIL.floor | Vincent Lejeune | 2012-10-10 | 1 | -1/+1 |
* | radeon/llvm: use llvm intrinsic for flog2 | Vincent Lejeune | 2012-10-10 | 1 | -1/+1 |
* | radeon/llvm: add support for cos/sin intrinsic | Vincent Lejeune | 2012-10-10 | 1 | -6/+11 |
* | radeon/llvm: add a pattern for fsqrt | Vincent Lejeune | 2012-10-10 | 1 | -0/+3 |
* | radeon/llvm: improve select_cc lowering to generate CND* more often | Vincent Lejeune | 2012-09-27 | 1 | -6/+32 |
* | radeon/llvm: support for interpolation intrinsics | Vincent Lejeune | 2012-09-22 | 1 | -0/+54 |
* | radeon/llvm: Handle loads from the constants address space. | Tom Stellard | 2012-09-21 | 1 | -0/+9 |
* | radeon/llvm: Add support for v4f32 stores on R600 | Tom Stellard | 2012-09-21 | 1 | -7/+23 |
* | radeon/llvm: Add support for i8 reads on R600 | Tom Stellard | 2012-09-21 | 1 | -0/+16 |
* | radeon/llvm: Emit ISA for ALU instructions in the R600 code emitter | Michal Sciubidlo | 2012-09-19 | 1 | -52/+108 |
* | radeon/llvm: Add a fdiv pattern. | Vincent Lejeune | 2012-09-18 | 1 | -3/+10 |
* | radeon/llvm: Fix lowering of vbuild | Tom Stellard | 2012-09-13 | 1 | -10/+10 |
* | radeon/llvm: Fix isEG tablegen predicate | Tom Stellard | 2012-08-31 | 1 | -3/+5 |
* | radeon/llvm: Cleanup R600Instructions.td | Tom Stellard | 2012-08-24 | 1 | -92/+28 |
* | radeon/llvm: Set End of Program bit on RAT instructions | Tom Stellard | 2012-08-23 | 1 | -7/+11 |
* | radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SI | Tom Stellard | 2012-08-23 | 1 | -0/+8 |
* | radeon/llvm: Mark JUMP as a pseudo instruction | Tom Stellard | 2012-08-23 | 1 | -1/+1 |
* | radeon/llvm: Add flag operand to some instructions | Tom Stellard | 2012-08-23 | 1 | -17/+39 |
* | radeon/llvm: ExpandSpecialInstrs - Add support for cube instructions | Tom Stellard | 2012-08-21 | 1 | -10/+21 |
* | radeon/llvm: Lower implicit parameters before ISel | Tom Stellard | 2012-08-16 | 1 | -18/+0 |
* | radeon/llvm: Add a predicated JUMP instruction | Vincent Lejeune | 2012-08-15 | 1 | -0/+9 |
* | radeon/llvm: Support for predicate bit | Vincent Lejeune | 2012-08-15 | 1 | -5/+24 |
* | radeon/llvm: Add live-in registers during DAG lowering | Tom Stellard | 2012-08-15 | 1 | -15/+0 |
* | radeon/llvm: Lower store_output intrinsic during DAG lowering | Tom Stellard | 2012-08-15 | 1 | -7/+0 |
* | radeon/llvm: Force VTX_READ instructions to use same reg for src and dst | Tom Stellard | 2012-08-15 | 1 | -0/+14 |
* | radeon/llvm: Remove CMOVLOG DAG node | Tom Stellard | 2012-08-02 | 1 | -2/+2 |
* | radeon/llvm: Rename all AMDIL* classes to AMDGPU* | Tom Stellard | 2012-07-30 | 1 | -7/+7 |
* | radeon/llvm: Move conditional pattern leafs to common tablegen file | Tom Stellard | 2012-07-27 | 1 | -41/+0 |
* | radeon/llvm: Use multiclasses for floating point loads | Tom Stellard | 2012-07-11 | 1 | -10/+32 |
* | radeon/llvm: Rename namespace from AMDIL to AMDGPU | Tom Stellard | 2012-07-09 | 1 | -2/+2 |
* | radeon/llvm: Enable vec4 loads on R600 | Tom Stellard | 2012-06-29 | 1 | -0/+16 |
* | radeon/llvm: Enable floating point stores on R600 | Tom Stellard | 2012-06-29 | 1 | -0/+6 |
* | radeon/llvm: Emit raw ISA for vertex fetch instructions | Tom Stellard | 2012-06-29 | 1 | -8/+94 |
* | radeon/llvm: Turn on the BitExtract peephole optimization | Tom Stellard | 2012-06-21 | 1 | -0/+21 |
* | radeon/llvm: Lower ROTL to BIT_ALIGN | Tom Stellard | 2012-06-21 | 1 | -0/+7 |
* | radeon/llvm: Fix sin/cos codegen on R700 | Török Edwin | 2012-06-19 | 1 | -19/+24 |
* | radeon/llvm: Emulate RECIP_UINT instruction on Cayman | Tom Stellard | 2012-06-06 | 1 | -4/+11 |
* | radeon/llvm: Fix MULLO* instructions on Cayman | Tom Stellard | 2012-06-06 | 1 | -7/+30 |
* | r600g: Compute support for Cayman | Tom Stellard | 2012-06-06 | 1 | -48/+44 |
* | radeon/llvm: Remove AMDIL VCREATE* instructions | Tom Stellard | 2012-06-06 | 1 | -0/+3 |
* | radeon/llvm: Remove AMDIL LOADCONST* instructions | Tom Stellard | 2012-06-06 | 1 | -1/+20 |
* | radeon/llvm: Fix VTX_READ patterns | Tom Stellard | 2012-06-01 | 1 | -3/+3 |
* | radeon/llvm: Remove AMDIL GLOBALSTORE* instructions | Tom Stellard | 2012-06-01 | 1 | -8/+13 |
* | radeon/llvm: Remove AMDIL GLOBALLOAD* instructions | Tom Stellard | 2012-06-01 | 1 | -95/+17 |
* | radeon/llvm: Use a custom inserter for MASK_WRITE | Tom Stellard | 2012-05-25 | 1 | -10/+22 |
* | radeon/llvm: Use tablegen pattern to lower bitconvert | Tom Stellard | 2012-05-25 | 1 | -0/+5 |
* | radeon/llvm: Use a custom inserter to lower FNEG | Tom Stellard | 2012-05-25 | 1 | -0/+1 |
* | radeon/llvm: Use a custom inserter to lower CLAMP | Tom Stellard | 2012-05-25 | 1 | -10/+1 |
* | radeon/llvm: Use a custom inserter to lower FABS | Tom Stellard | 2012-05-25 | 1 | -1/+1 |