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path: root/src/gallium/drivers/radeon/AMDILISelLowering.cpp
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* radeon/llvm: Remove backend code from MesaTom Stellard2013-01-041-677/+0
* radeon/llvm: Fix lowering of vbuildTom Stellard2012-09-131-68/+0
* radeon/llvm: Remove CMOVLOG DAG nodeTom Stellard2012-08-021-68/+1
* radeon/llvm: Rename all AMDIL* classes to AMDGPU*Tom Stellard2012-07-301-2/+2
* radeon/llvm: Merge AMDILSubtarget into AMDGPUSubtargetTom Stellard2012-07-301-2/+2
* radeon/llvm: Merge AMDILTargetLowering class into AMDGPUTargetLoweringTom Stellard2012-07-301-95/+38
* radeon/llvm: Remove IL_cmp DAG nodeTom Stellard2012-07-301-340/+2
* radeon/llvm: Remove lowering code for unsupported featuresTom Stellard2012-07-301-575/+0
* radeon/llvm: Merge AMDILRegisterInfo into AMDGPURegisterInfoTom Stellard2012-07-301-1/+1
* radeon/llvm: Move lowering of BR_CC node to R600ISelLoweringTom Stellard2012-07-271-29/+0
* radeon/llvm: Move lowering of SETCC node to R600ISelLoweringTom Stellard2012-07-271-35/+0
* radeon/llvm: Use correct node type when lowering SETCCTom Stellard2012-07-271-0/+1
* radeon/llvm: Fix a bug with IF LOGICALNZ with int operandVincent Lejeune2012-07-231-2/+2
* radeon/llvm: Rename namespace from AMDIL to AMDGPUTom Stellard2012-07-091-2/+2
* radeon/llvm: Lower ROTL to BIT_ALIGNTom Stellard2012-06-211-1/+0
* radeon/llvm: Remove unused AMDIL TableGen definitonsTom Stellard2012-06-181-508/+2
* radeon/llvm: Eliminate getRegClassFromType() functionTom Stellard2012-06-181-42/+1
* radeon/llvm: Remove deadcode from AMDILISelLowering.cppTom Stellard2012-06-181-1609/+0
* radeon/llvm: Remove AMDIL MOVE* instructionsTom Stellard2012-06-061-2/+0
* radeon/llvm: Remove deadcode from the AMDILISelLowering classTom Stellard2012-06-061-119/+0
* radeon/llvm: Remove AMDIL LOADCONST* instructionsTom Stellard2012-06-061-37/+0
* radeon/llvm: Change prefix on tablegen files to AMDGPUTom Stellard2012-06-011-1/+1
* radeonsi: Handle TGSI CONST registersTom Stellard2012-05-291-1/+0
* radeon/llvm: Remove AMDILTargetMachineTom Stellard2012-05-291-59/+33
* radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard2012-05-251-285/+0
* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-241-32/+0
* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-241-75/+0
* radeon/llvm: Remove AMDIL FTOI and ITOF instructionsTom Stellard2012-05-241-162/+0
* radeon/llvm: Remove AMDIL ADD instructionsTom Stellard2012-05-241-169/+0
* radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard2012-05-241-81/+0
* radeon/llvm: Remove AMDIL CMP instructions and associated lowering codeTom Stellard2012-05-241-650/+22
* radeon/llvm: fix BUILD_VECTOR lowering for replicated valueVadim Girlin2012-05-151-0/+2
* radeon/llvm: Remove AMDILUtilityFunctions.cppTom Stellard2012-05-081-3/+44
* r600g/llvm: Remove unnecessary dynamic castsDragomir Ivanov2012-04-301-5/+5
* radeon/llvm: Remove AMDILMachineFunctionInfo.cppTom Stellard2012-04-251-5/+0
* radeon/llvm: Remove GlobalManager and KernelManagerTom Stellard2012-04-251-52/+21
* radeonsi: initial WIP SI codeTom Stellard2012-04-131-0/+5612
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