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path: root/src/gallium/drivers/r600/evergreen_hw_context.c
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* gallium: add PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE to skip util_range lockMarek Olšák2019-10-071-2/+2
| | | | | | | | | u_upload_mgr sets it, so that util_range_add can skip the lock. The time spent in tc_transfer_flush_region decreases from 0.8% to 0.2% in torcs on radeonsi. Reviewed-by: Kenneth Graunke <[email protected]>
* r600/eg: rework atomic counter emission with flushesDave Airlie2018-08-211-1/+1
| | | | | | | | | | | | | | | | | | | | With the current code, we didn't do the space checks prior to atomic counter setup emission, but we also didn't add atomic counters to the space check so we could get a flush later as well. These flushes would be bad, and lead to problems with parallel tests. We have to ensure the atomic counter copy in, draw emits and counter copy out are kept in the same command submission unit. This reworks the code to drop some useless masks, make the counting separate to the emits, and make the space checker handle atomic counter space. [airlied: want this in 18.2] Fixes: 06993e4ee (r600: add support for hw atomic counters. (v3))
* r600: fix build after the removal of RADEON_PRIO_* flagsMarek Olšák2018-07-161-4/+2
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* amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbufMarek Olšák2018-06-191-2/+2
| | | | Acked-by: Bas Nieuwenhuizen <[email protected]>
* gallium/radeon: prevent SDMA stalls by detecting RAW hazards in need_dma_spaceMarek Olšák2017-01-051-1/+0
| | | | | | | | Call r600_dma_emit_wait_idle only when there is a possibility of a read-after-write hazard. Buffers not yet used by the SDMA IB don't have to wait. Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: only do necessary cache flushes in cp_dma_clear_bufferMarek Olšák2016-06-041-14/+1
| | | | | | | | The main impact is that fast color clear doesn't flush TC, CONST, DB. Reviewed-by: Alex Deucher <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* r600g: fix CP DMA hazard with index buffer fetches (v3)Marek Olšák2016-06-041-3/+13
| | | | | | | | | v3: use PFP_SYNC_ME on EG-CM only when supported by the kernel, otherwise use MEM_WRITE + WAIT_REG_MEM to emulate that Reviewed-by: Alex Deucher <[email protected]> Tested-by: Grazvydas Ignotas <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/radeon: use radeon_emitNicolai Hähnle2016-05-171-5/+5
| | | | | | | Mostly generated using a sed-script, with manual fix-up for multi-line statements. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: flush if DMA IB memory usage is too highMarek Olšák2016-05-101-1/+1
| | | | | | | | This prevents IB rejections due to insane memory usage from many concecutive texture uploads. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: fix (S)DMA read-after-write hazardsMarek Olšák2016-05-101-0/+1
| | | | | Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: inline the r600_rings structureMarek Olšák2015-11-131-5/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: tell the winsys the exact resource binding typesMarek Olšák2015-10-031-3/+3
| | | | | | | Use the priority flags and expand them. This information will be used for debugging. Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: rename r600_context_bo_reloc -> radeon_add_to_buffer_listMarek Olšák2015-09-011-3/+3
| | | | | | | this name should be easy to understand without other knowledge Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* Fix a few typosZoë Blade2015-04-271-1/+1
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* r600g: use gpu_address from r600_resourceMarek Olšák2014-08-091-3/+3
| | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: use more appropriate names for async DMA functionsMarek Olšák2014-03-201-6/+6
| | | | | | *_dma_copy calls either *_dma_copy_buffer or *_dma_copy_tile. Reviewed-by: Michel Dänzer <[email protected]>
* r600g: deobfuscate async DMA codeMarek Olšák2014-03-201-5/+5
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g: don't flush the gfx IB explicitly before doing DMAMarek Olšák2014-03-201-2/+0
| | | | | | It's flushed by calling r600_context_bo_reloc. Reviewed-by: Michel Dänzer <[email protected]>
* radeon: Move r600_need_dma_space to common codeNiels Ole Salscheider2014-03-201-1/+1
| | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g,radeonsi: set priorities for relocationsMarek Olšák2014-03-111-3/+6
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* r600g,radeonsi: fix initialized buffer range tracking for DMA, add commentsMarek Olšák2013-12-121-6/+12
| | | | | | | The DMA functions modify dst_offset and size and util_range_add gets wrong values. Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: share flags has_cp_dma and has_streamoutMarek Olšák2013-12-121-1/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* Revert "r600g: only flush the caches that need to be flushed during CP DMA ↵Marek Olšák2013-10-061-5/+14
| | | | | | | | | | | | | | | | | operations" This reverts commit 7948ed1250cae78ae1b22dbce4ab23aceacc6159. It caused graphical corruption. I've got no idea why. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70042 https://bugs.freedesktop.org/show_bug.cgi?id=68451 Conflicts: src/gallium/drivers/r600/evergreen_hw_context.c src/gallium/drivers/r600/r600_hw_context.c src/gallium/drivers/r600/r600_pipe.h
* r600g: move streamout state to drivers/radeonMarek Olšák2013-08-311-51/+20
| | | | | | | | | | | | | | | | | | | | | | | | This streamout state code will be used by radeonsi. There are new structures r600_common_context and r600_common_screen. What is inherited by what is shown here: pipe_context -> r600_common_context -> r600_context pipe_screen -> r600_common_screen -> r600_screen The common structures reside in drivers/radeon. Currently they only contain enough functionality to be able to handle streamout. Eventually I'd like the whole pipe_screen implementation to be shared and some of the context stuff too. This is quite big, but most changes are because of the new structures and the fact r600_write_value is replaced by radeon_emit. Thanks to Tom Stellard for fixing the build for r600g/compute. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Tested-by: Tom Stellard <[email protected]>
* r600g: use WAIT_3D_IDLE before using CP DMAMarek Olšák2013-07-181-0/+1
| | | | I broke this with 7948ed1250cae78ae1b22dbce4ab23aceacc6159 for r700 at least.
* r600g: only flush the caches that need to be flushed during CP DMA operationsMarek Olšák2013-07-081-16/+5
| | | | | | | This should increase performance if constant uploads are done with the CP DMA, because only the cache that needs to be flushed is flushed. Reviewed-by: Alex Deucher <[email protected]>
* r600g: split INVAL_READ_CACHES into vertex, tex, and const cache flagsMarek Olšák2013-07-081-2/+6
| | | | | | | also flushing any cache in evergreen_emit_cs_shader seems to be superfluous (we don't flush caches when changing the other shaders either) Reviewed-by: Alex Deucher <[email protected]>
* r600g: adjust flush flags (v3)Alex Deucher2013-07-081-0/+2
| | | | | | | | | | | | | 1. flush SH with read caches 2. add flag for DB flushes 3. add flag for CB flushes v2: flush all CBs, remove redundant emit_state variable. v3: Marek: also set the new flags in r600_context_flush, the CP dma functions, and texture_barrier, and rename them Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: use CP DMA for buffer clears on evergreen+Alex Deucher2013-04-241-0/+66
| | | | | | | | | | Lighter weight then using streamout. Only evergreen and newer asics support embedded data as src with CP DMA. Reviewed-by: Jerome Glisse <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* r600g: remove r600_hw_context_priv.h, move the stuff to r600_pipe.hMarek Olšák2013-03-111-1/+1
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: remove deprecated state management codeMarek Olšák2013-03-111-16/+0
| | | | | | It's nice to see so much code that did pretty much nothing go away. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize pixel shaderMarek Olšák2013-03-111-96/+0
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize vertex shaderMarek Olšák2013-03-111-27/+0
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: always map uninitialized buffer range as unsynchronizedMarek Olšák2013-03-011-0/+3
| | | | | | | | | | Any driver can implement this simple and efficient optimization. Team Fortress 2 hits it always. The DISCARD_RANGE codepath is not even used with TF2 anymore, so we avoid a ton of useless buffer copies. Tested-by: Andreas Boll <[email protected]> NOTE: This is a candidate for the 9.1 branch.
* r600g: cleanup deprecated register tablesMarek Olšák2013-03-011-42/+0
| | | | | | These registers are either already emitted elsewhere or moved to start_cs. Tested-by: Andreas Boll <[email protected]>
* r600g: use uint64_t instead of unsigned long for proper 32bits cpu supportJerome Glisse2013-01-281-3/+3
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add async for staging buffer upload v2Jerome Glisse2013-01-281-0/+46
| | | | | | v2: Add virtual address to dma src/dst offset for cayman Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add multi ring support with dma as first second ring v4Jerome Glisse2013-01-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | We keep track of ring emission order in a stack, whenever we need to flush we empty the stack in a fifo order. There is few helpers function for bo mapping and other ring activities that will make sure that the ring stack is properly flush and submitted. v2: fix st flush path, and other flush path to properly flush all rings if necessary v3: - improve name of ring helpers - make sure that each time a cs is gona be written it endup at top of the stack to avoid any issue such as : STACK[0] = dma (withbo A,B) STACK[1] = gfx (withbo C,D) Now if code try to emit a dma command relative to bo C or D it will start writting cmd stream into the cs and once it reach the point where it adds relocation it will flush. At that point the cs will have cmd that don't have proper relocation into the relocation buffer and kernel will just refuse to run. v4: - Drop the stack idea as it turn out there is no way to use it or benefit from it. Any time the driver start command on other ring, it always need to flush the previous ring. So make code simpler by not using a stack. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: move DB_SHADER_CONTROL into db_misc_stateMarek Olšák2012-10-101-2/+0
| | | | | | | Also update the register value in more appropriate places than r600_update_derived_state. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize depth-stencil-alpha stateMarek Olšák2012-10-101-2/+0
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize rasterizer stateMarek Olšák2012-10-101-18/+0
| | | | Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize scissor stateMarek Olšák2012-10-101-4/+0
| | | | | | The workaround for R600 lacking VPORT_SCISSOR_ENABLE has also been simplified. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize polygon offset stateMarek Olšák2012-10-101-10/+0
| | | | | | | POLY_OFFSET_DB_FMT_CNTL is moved to the framebuffer state, because it only depends on the zbuffer format. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize fetch shaderMarek Olšák2012-10-101-2/+0
| | | | | | | The state object is actually a buffer, it's literally a buffer containing the shader code. Reviewed-by: Jerome Glisse <[email protected]>
* r600g: atomize blend stateMarek Olšák2012-10-101-20/+0
| | | | | | | | | | | This is not so trivial, because we disable blending if the dual src blending is turned on and the number of color outputs is less than 2. I decided to create 2 command buffers in the blend state object and just switch between them when needed, because there are other states unrelated to blending (like the color mask) and those shouldn't be changed (the old code had it wrong). Reviewed-by: Jerome Glisse <[email protected]>
* r600g: use CS helpers to emit streamout stateMarek Olšák2012-09-221-13/+5
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove initialization of unused loop register tablesMarek Olšák2012-09-221-19/+0
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove now-unused SURFACE_BASE_UPDATE logicMarek Olšák2012-09-221-1/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove unused CB registers from register listsMarek Olšák2012-09-221-80/+0
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: atomize framebuffer stateMarek Olšák2012-09-221-304/+0
| | | | | | Tested on RS880, Evergreen and Cayman. Reviewed-by: Alex Deucher <[email protected]>
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