diff options
| author | Marek Olšák <[email protected]> | 2016-05-26 22:00:03 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-06-04 15:42:33 +0200 |
| commit | 5ea5ed60500a8612166853975b42abd40a459216 (patch) | |
| tree | 5b9bc8656166ed7b359b3ceca87c54591a3bdb6e /src/gallium/drivers/r600/evergreen_hw_context.c | |
| parent | ade16e1f5d046f6407c4f0046efb8363520adcf0 (diff) | |
r600g: fix CP DMA hazard with index buffer fetches (v3)
v3: use PFP_SYNC_ME on EG-CM only when supported by the kernel,
otherwise use MEM_WRITE + WAIT_REG_MEM to emulate that
Reviewed-by: Alex Deucher <[email protected]>
Tested-by: Grazvydas Ignotas <[email protected]>
Tested-by: Dieter Nützel <[email protected]>
Diffstat (limited to 'src/gallium/drivers/r600/evergreen_hw_context.c')
| -rw-r--r-- | src/gallium/drivers/r600/evergreen_hw_context.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c index f456696970c..2feb8015082 100644 --- a/src/gallium/drivers/r600/evergreen_hw_context.c +++ b/src/gallium/drivers/r600/evergreen_hw_context.c @@ -85,7 +85,8 @@ void evergreen_dma_copy_buffer(struct r600_context *rctx, void evergreen_cp_dma_clear_buffer(struct r600_context *rctx, struct pipe_resource *dst, uint64_t offset, - unsigned size, uint32_t clear_value) + unsigned size, uint32_t clear_value, + enum r600_coherency coher) { struct radeon_winsys_cs *cs = rctx->b.gfx.cs; @@ -117,7 +118,9 @@ void evergreen_cp_dma_clear_buffer(struct r600_context *rctx, unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT); unsigned reloc; - r600_need_cs_space(rctx, 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0), FALSE); + r600_need_cs_space(rctx, + 10 + (rctx->b.flags ? R600_MAX_FLUSH_CS_DWORDS : 0) + + R600_MAX_PFP_SYNC_ME_DWORDS, FALSE); /* Flush the caches for the first copy only. */ if (rctx->b.flags) { @@ -148,9 +151,16 @@ void evergreen_cp_dma_clear_buffer(struct r600_context *rctx, offset += byte_count; } + /* CP DMA is executed in ME, but index buffers are read by PFP. + * This ensures that ME (CP DMA) is idle before PFP starts fetching + * indices. If we wanted to execute CP DMA in PFP, this packet + * should precede it. + */ + if (coher == R600_COHERENCY_SHADER) + r600_emit_pfp_sync_me(rctx); + /* Invalidate the read caches. */ rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE | R600_CONTEXT_INV_VERTEX_CACHE | R600_CONTEXT_INV_TEX_CACHE; } - |