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* nouveau: remove unused class memberEric Engestrom2018-10-301-1/+0
* util: Change remaining uint32 cache ids to sha1David McFarland2018-10-261-14/+15
* nvc0: increase NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD to 1024 on Kepler+Rhys Perry2018-10-254-3/+11
* nv50/ir: fix ConstantFolding::createMul for 64 bit mulsKarol Herbst2018-10-201-1/+1
* nvc0: fix blitting red to srgb8_alphaIlia Mirkin2018-10-091-0/+4
* nv50,nvc0: guard against zero-size blitsIlia Mirkin2018-10-092-0/+14
* nv50,nvc0: mark RGBX_UINT formats as renderableIlia Mirkin2018-10-091-4/+4
* nouveau: use build-id when available for disk cacheTimothy Arceri2018-10-031-7/+7
* nv50/ir: fix link-time build failureRhys Perry2018-09-231-1/+1
* nvc0: fix bindless multisampled images on Maxwell+Rhys Perry2018-09-223-5/+45
* nvc0: warn about changing NVC0_CB_AUX_MP_INFO and NVC0_CB_AUX_DRAW_INFORhys Perry2018-09-221-2/+6
* nvc0: Update counter reading shaders to new NVC0_CB_AUX_MP_INFORhys Perry2018-09-221-18/+18
* nvir: Always split 64-bit IMAD/IMUL operationsPierre Moreau2018-09-131-1/+1
* nv50,nvc0: warn on not-explicitly-handled capsIlia Mirkin2018-09-112-14/+26
* gallium: add PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGETMarek Olšák2018-09-073-0/+3
* gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsiMarek Olšák2018-09-063-0/+3
* gallium: split depth_clip into depth_clip_near & depth_clip_farMarek Olšák2018-09-063-3/+3
* gallium: Add a helper for implementing PIPE_CAP_* default values.Eric Anholt2018-09-043-9/+9
* nv50: bump compat glsl level to same as coreIlia Mirkin2018-08-291-1/+1
* nvc0: bump compat GLSL version to match coreIlia Mirkin2018-08-291-1/+1
* nv50/ir: silence partitionLoadStore() unused function warningRhys Kidd2018-08-291-2/+2
* nv50/ir,nvc0: use constant buffers for compute when possible on Kepler+Rhys Perry2018-08-272-10/+36
* nv50/ir: optimize multiplication by 16-bit immediates into two xmadsRhys Perry2018-08-271-0/+10
* nv50/ir: optimize near power-of-twos into shladdRhys Perry2018-08-271-0/+27
* nv50/ir: move a * b -> a << log2(b) code into createMul()Rhys Perry2018-08-271-15/+30
* nv50/ir: optimize imul/imad to xmadsRhys Perry2018-08-272-1/+56
* gm107/ir: add support for OP_XMAD on GM107+Rhys Perry2018-08-273-1/+71
* nv50/ir: add preliminary support for OP_XMADRhys Perry2018-08-277-5/+85
* gallium: Split out PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE.Kenneth Graunke2018-08-243-0/+3
* gallium: add PIPE_CAP_MAX_SHADER_BUFFER_SIZEMarek Olšák2018-08-233-0/+6
* gallium: add PIPE_CAP_MAX_GS_INVOCATIONSMarek Olšák2018-08-233-0/+6
* nvc0/ir: return 0 in imageLoad on incomplete texturesKarol Herbst2018-08-042-3/+31
* gm200/ir: optimize rcp(sqrt) to rsqKarol Herbst2018-08-041-1/+10
* gm200/ir: add native OP_SQRT supportKarol Herbst2018-08-044-2/+14
* gallium: add storage_sample_count parameter into is_format_supportedMarek Olšák2018-07-314-0/+13
* gallium: add PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTSMarek Olšák2018-07-313-0/+3
* nvc0: serialize before updating some constant buffer bindings on Maxwell+Rhys Perry2018-07-304-47/+81
* nv50/ir: move LateAlgebraicOpt back to right after ConstantFoldingRhys Perry2018-07-191-1/+1
* nv50/ir: handle SHLADD in IndirectPropagationRhys Perry2018-07-191-0/+12
* gm107/ir: use CS2R for SV_CLOCKRhys Perry2018-07-193-2/+25
* nouveau: fix 3D blitter for unsigned to signed integer conversionsKarol Herbst2018-07-152-10/+22
* nv50/ir: fix Instruction::isActionEqual for PHI instructionsKarol Herbst2018-07-071-0/+6
* nvc0/ir: use the combined tid special registerRhys Perry2018-07-079-0/+61
* nvc0: implement multisampled images on Maxwell+Rhys Perry2018-07-046-39/+48
* nv50/ir: handle clipvertex for geom and tess shaders as wellKarol Herbst2018-07-021-1/+6
* gallium/util: remove dummy function util_format_is_supportedMarek Olšák2018-06-293-10/+0
* nv50/ir: improve maintainability of Target*::initOpInfo()Rhys Perry2018-06-292-23/+28
* nv50/ir: fix image stores with indirect handlesRhys Perry2018-06-291-4/+5
* nvc0: remove magic values in nve4_set_tex_handles()Rhys Perry2018-06-281-1/+1
* nvc0/ir: fix TargetNVC0::insnCanLoadOffset()Rhys Perry2018-06-281-0/+1
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