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path: root/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
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* nv50/ir: allow to swap sources for OP_SUBSamuel Pitoiset2016-07-221-1/+6
* nv50: fix alphatest for non-blendable formatsIlia Mirkin2016-07-161-0/+4
* nvc0/ir: handle a load's reg result not being used for locked variantsIlia Mirkin2016-05-261-2/+8
* Treewide: Remove Elements() macroJan Vesely2016-05-171-1/+1
* nouveau: codegen: combineLd/St do not combine indirect loadsHans de Goede2016-04-251-0/+7
* nv50/ir: do not try to attach JOIN ops to ATOMSamuel Pitoiset2016-04-071-1/+1
* nv50/ir: avoid folding mul + add if the mul has a dnzIlia Mirkin2016-03-131-3/+2
* nv50/ir: we can't do the add to mad conversion when the mul saturatesKarol Herbst2016-02-161-0/+3
* nv50/ir: optimize neg(and(set, 1)) to setKarol Herbst2016-02-161-0/+32
* nv50/ir: get rid of memory stores with nop valuesIlia Mirkin2016-01-301-0/+6
* nv50/ir: fix false global CSE on instructions with multiple defsIlia Mirkin2016-01-301-0/+2
* nv50/ir: add support for BUFFER accessesIlia Mirkin2016-01-291-1/+1
* nv50/ir: optimize mad/fma with third argument 0 to mulKarol Herbst2016-01-281-0/+21
* nv50/ir: run DCE backwardsKarol Herbst2016-01-281-3/+3
* nv50/ir: optimize shl(shr(a, c), c) to and(a, ~((1 << c) - 1))Karol Herbst2016-01-281-0/+8
* nv50/ir: don't flip SHL(ADD) into ADD(SHL) if ADD sources have modifiersIlia Mirkin2016-01-201-0/+2
* nv50/ir: swap the least-ref'd source into src1 when both const/immIlia Mirkin2016-01-181-10/+15
* nv50/ir: attempt to do more constant folding on mad -> add conversionIlia Mirkin2015-12-301-11/+10
* nv50/ir: float(s32 & 0xff) = float(u8), not s8Ilia Mirkin2015-12-291-0/+3
* nv50/ir: combine sequences of conversionsIlia Mirkin2015-12-121-0/+43
* nv50/ir: teach post-ra immediate folding into mad about integersIlia Mirkin2015-12-121-3/+31
* nv50/ir: add short imad supportIlia Mirkin2015-12-121-2/+4
* nv50/ir: can't have predication and immediatesIlia Mirkin2015-12-121-0/+3
* nv50/ir: fix assumption that prog->maxGPR is in 32-bit reg unitsIlia Mirkin2015-12-121-3/+20
* nv50/ir: check if the target supports the new offset before inliningIlia Mirkin2015-12-081-3/+6
* nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integersIlia Mirkin2015-12-071-5/+11
* nv50/ir: fold shl + mul with immediatesIlia Mirkin2015-12-051-0/+16
* nv50/ir: propagate indirect loads into instructionsIlia Mirkin2015-12-051-0/+52
* nv50/ir: flip shl(add, imm) into add(shl, imm)Ilia Mirkin2015-12-051-4/+34
* nv50/ir: fold fma/mad when all 3 args are immediatesIlia Mirkin2015-12-031-0/+30
* nv50/ir: fix DCE to not generate 96-bit loadsIlia Mirkin2015-12-031-1/+31
* nv50/ir: the mad source might not have a defining instructionIlia Mirkin2015-12-021-1/+1
* nvc0/ir: fold postfactor into immediateIlia Mirkin2015-12-021-0/+6
* nv50/ir: properly set the type of the constant folding resultIlia Mirkin2015-11-061-4/+4
* nv50/ir: add support for const-folding OP_CVT with F64 source/destIlia Mirkin2015-11-061-0/+31
* nv50/ir: Add support for 64bit immediates to checkSwapSrc01Hans de Goede2015-11-061-5/+6
* nv50/ir: Add support for merge-s to the ConstantFolding passHans de Goede2015-11-061-0/+15
* nv50/ir: don't fold immediate into mad if registers are too highIlia Mirkin2015-09-101-0/+4
* nv50/ir: Handle OP_CVT when folding constant expressionsTobias Klausmann2015-08-201-0/+78
* nvc0/ir: undo more shifts still by allowing a pre-SHL to occurIlia Mirkin2015-08-201-15/+33
* nvc0/ir: don't require AND when the high byte is being addressedIlia Mirkin2015-08-201-0/+12
* nvc0/ir: detect i2f/i2i which operate on specific bytes/wordsIlia Mirkin2015-08-201-4/+75
* nvc0/ir: detect AND/SHR pairs and convert into EXTBFIlia Mirkin2015-08-201-20/+46
* nvc0/ir: per-patch vars are in a separate address spaceIlia Mirkin2015-07-241-0/+2
* nvc0/ir: allow tess eval output loads to be CSE'dIlia Mirkin2015-07-231-0/+2
* nv50/ir: propagate modifier to right arg when const-folding madIlia Mirkin2015-06-261-1/+4
* nvc0/ir: can't have a join on a load with an indirect sourceIlia Mirkin2015-06-171-1/+1
* nv50/ir: avoid messing up arg1 of PFETCHIlia Mirkin2015-05-231-2/+18
* nv50/ir: allow OP_SET to merge with OP_SET_AND/etc as well as a negIlia Mirkin2015-05-221-26/+55
* nvc0/ir: optimize set & 1.0 to produce boolean-float setsIlia Mirkin2015-05-221-0/+27
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