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path: root/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
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* nvc0/ir: use the combined tid special registerRhys Perry2018-07-071-0/+12
* nvc0: implement multisampled images on Maxwell+Rhys Perry2018-07-041-29/+2
* nvc0: add support for programmable sample locationsRhys Perry2018-06-141-10/+92
* nvir/nvc0: fix legalizing of ld unlock c0[0x10000]Karol Herbst2018-02-211-1/+1
* nvc0: add support for bindless on maxwell+Ilia Mirkin2018-02-171-9/+23
* nvc0: add bindless image support for keplerIlia Mirkin2018-01-071-26/+31
* nvc0: add support for bindless textures on kepler+Ilia Mirkin2018-01-071-4/+6
* nvc0/ir: safen up lowering logic against overwriting reused valuesIlia Mirkin2018-01-071-2/+4
* nvc0/ir: change textureGrad to always use lane 0 as the tex originIlia Mirkin2017-12-191-14/+46
* nvc0/ir: Properly lower 64-bit shifts when the shift value is >32Pierre Moreau2017-12-041-1/+1
* nvc0/ir: propagate immediates to CALL input MOVsTobias Klausmann2017-08-311-2/+19
* nvc0/ir: unlink values pre- and post-call to division functionIlia Mirkin2017-08-121-4/+3
* nvc0/ir: SHLADD's middle source must be an immediateIlia Mirkin2017-05-201-0/+2
* nvc0/ir: fix ubo max clamp, reset file indexIlia Mirkin2017-02-091-1/+3
* nvc0/ir: fix robustness guarantees for constbuf loads on kepler+ computeIlia Mirkin2017-02-091-25/+22
* nvc0/ir: make it possible to have the flags def in def0Ilia Mirkin2017-02-091-1/+1
* nvc0/ir: add support for 64-bit shift lowering on SM20/SM30Ilia Mirkin2017-02-091-6/+62
* nvc0/ir: add support for all the new int64 tgsi opcodesIlia Mirkin2017-02-091-1/+66
* nvc0: enable FBFETCH with a special slot for color buffer 0Ilia Mirkin2017-01-161-4/+16
* nvc0/ir: only try to check for zero LOD if we aren't already forcing itIlia Mirkin2017-01-121-1/+1
* nv50/ir: do not insert texture barriers on gm107Samuel Pitoiset2017-01-121-1/+2
* nvc0/ir: use levelZero flag when the lod is set to 0Ilia Mirkin2016-11-201-6/+42
* nvc0/ir: simplify predicate logic for GK104 atomic operationsSamuel Pitoiset2016-10-191-14/+7
* nvc0/ir: remove useless NVC0LoweringPass::gMemBaseSamuel Pitoiset2016-10-191-4/+1
* gm107/ir: fix texturing with indirect samplersIlia Mirkin2016-10-181-0/+10
* nvc0/ir: fix textureGather with a single offsetIlia Mirkin2016-10-121-2/+2
* nvc0/ir: fix overwriting of value backing non-constant gather offsetIlia Mirkin2016-10-101-2/+2
* gm107/ir: allow indirect inputs to be loaded by frag shaderIlia Mirkin2016-09-101-4/+21
* gm107/ir: lower surface operationsSamuel Pitoiset2016-07-201-1/+75
* nvc0: add support for BGRA8 imagesIlia Mirkin2016-07-181-0/+4
* nvc0/ir: fix images indirect access on FermiSamuel Pitoiset2016-07-111-0/+7
* nvc0/ir: remove unused resource info loading helpersSamuel Pitoiset2016-07-081-24/+0
* nvc0/ir: refactor the surfaces info loading logicSamuel Pitoiset2016-07-081-81/+43
* nvc0/ir: move the shift left op inside loadTexHandle()Samuel Pitoiset2016-07-081-8/+6
* nvc0/ir: rename NVE4_SU_INFO_XXX to NVC0_SU_INFO_XXXSamuel Pitoiset2016-07-051-49/+49
* nvc0/ir: reset the base offset for indirect images accessesSamuel Pitoiset2016-07-051-2/+4
* nouveau: Add support for SV_WORK_DIMHans de Goede2016-07-021-0/+2
* nvc0: fix up image support for allowing multiple samplesIlia Mirkin2016-07-011-32/+48
* gk104/ir: fix tex use generation to be more careful about eliding usesIlia Mirkin2016-06-191-10/+24
* nvc0/ir: clamp the UBO index for compute on KeplerSamuel Pitoiset2016-06-131-1/+9
* gk104/ir: fix conditions for adding a texbarIlia Mirkin2016-06-071-4/+6
* nvc0/ir: limit max number of regs based on availability in SMIlia Mirkin2016-05-301-1/+1
* nvc0/ir: avoid generating illegal instructions for compute constbuf loadsIlia Mirkin2016-05-261-1/+2
* nvc0/ir: fix indirect access for imagesSamuel Pitoiset2016-05-221-8/+14
* nvc0/ir: return 0 for gl_TessCoord.z for non-triangles modesIlia Mirkin2016-05-221-0/+4
* nvc0/ir: add a lowering pass for surfaces on FermiSamuel Pitoiset2016-05-211-0/+115
* nvc0/ir: don't check the format for surface stores on KeplerSamuel Pitoiset2016-05-211-8/+7
* nvc0/ir: fix shared atomic lowering to preserve shared memory locationIlia Mirkin2016-05-171-10/+8
* nvc0/ir: make sure out-of-bounds buffer loads/atomics get a 0 resultIlia Mirkin2016-05-171-1/+26
* nvc0/ir: make sure to align the second arg of TXD to 4, as we do for TEXIlia Mirkin2016-05-151-0/+14
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