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path: root/src/freedreno/registers/a6xx.xml
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* freedreno/a6xx: Add stencilref register infoConnor Abbott2020-07-161-1/+2
* freedreno/regs: update a6xx PC regsJonathan Marek2020-07-141-47/+57
* freedreno/regs: update a6xx VPC regsJonathan Marek2020-07-141-29/+41
* freedreno/regs: update a6xx RB regsJonathan Marek2020-07-141-98/+154
* freedreno/regs: update a6xx GRAS registersJonathan Marek2020-07-141-97/+126
* freedreno/a6xx: Add some documentation for shared constsConnor Abbott2020-07-141-2/+22
* freedreno/a6xx: Rename and document HLSQ_UPDATE_CNTLConnor Abbott2020-07-141-2/+25
* freedreno/registers: Rename SP_2D_SRC_FORMATKristian H. Kristensen2020-07-141-4/+1
* freedreno/regs: update primitive output related registersJonathan Marek2020-07-141-95/+51
* freedreno/regs: document CS shared storage size bitJonathan Marek2020-07-081-1/+10
* freedreno: Sync registers with envytoolsConnor Abbott2020-07-071-3/+101
* freedreno/registers: update varying-related registersJonathan Marek2020-07-011-9/+12
* freedreno/regs: add extra bits for UBWC array pitchJonathan Marek2020-06-291-2/+2
* freedreno/a6xx: Define the register fields for polygon fill mode.Eric Anholt2020-06-251-2/+13
* freedreno/registers: a6xx depth bounds test registersJonathan Marek2020-06-241-5/+7
* turnip: Support tess for drawsBrian Ho2020-06-221-0/+1
* freedreno/a6xx: VSC "STRM_ARRAY_PITCH" is "STRM_LIMIT"Jonathan Marek2020-06-201-2/+4
* freedreno/a6xx: FETCHSIZE is PITCHALIGNJonathan Marek2020-06-181-9/+2
* turnip: Add support for alphaToOne.Eric Anholt2020-06-051-0/+1
* freedreno/a6xx: update depth-plane control regsRob Clark2020-06-041-2/+40
* freedreno/a6xx: sync registers from envytoolsRob Clark2020-06-041-1/+8
* freedreno/a6xx: document LRZ flag bufferRob Clark2020-05-291-1/+32
* freedreno: Use explicit *_NONE enum for undefined formatsKristian H. Kristensen2020-05-261-0/+4
* freedreno/registers: document 422_UNORM and 420_UNORM formatsJonathan Marek2020-05-201-1/+26
* freedreno/a6xx: Document dual-src blending enable bitsConnor Abbott2020-05-141-0/+4
* freedreno,tu: Don't request fragcoord components not being read.Hyunjun Ko2020-05-081-8/+2
* freedreno: sync registers with envytoolsRob Clark2020-04-301-8/+20
* freedreno/a6xx+tu: rename VSC_DATA/VSC_DATA2Rob Clark2020-04-281-33/+23
* freedreno/a6xx: Document PrimID passthrough registersConnor Abbott2020-04-251-1/+14
* turnip: implement VK_EXT_sampler_filter_minmaxJonathan Marek2020-04-221-1/+8
* turnip: implement VK_EXT_filter_cubicJonathan Marek2020-04-221-0/+1
* turnip: implement VK_EXT_sample_locationsJonathan Marek2020-04-221-14/+25
* freedreno/a6xx: Expand various varying-count bitfieldsConnor Abbott2020-04-211-6/+6
* freedreno/turnip: Update GRAS_LAYER_CNTL to GRAS_MAX_LAYER_INDEXBrian Ho2020-04-151-4/+2
* freedreno/a6xx: Add registers for the bindless modelConnor Abbott2020-04-091-0/+38
* freedreno/a6xx: Add UBO size fieldConnor Abbott2020-04-091-1/+1
* turnip: new clear/blit implementation with shader path fallbackJonathan Marek2020-04-091-1/+6
* freedreno/registers: add RB_CCU_CNTL bitfieldsJonathan Marek2020-04-091-1/+13
* turnip: improve vertex input handlingJonathan Marek2020-04-091-2/+4
* freedreno/a6xx: register updateRob Clark2020-03-271-1/+3
* freedreno/registers: more GRAS_CL_CNTL bits, Z_CLAMPJonathan Marek2020-03-241-3/+17
* tu: Fix border color with compute shadersConnor Abbott2020-03-171-0/+6
* turnip: add r5g5b5a1_unorm/b5g5r5a1_unorm formatsJonathan Marek2020-02-281-0/+1
* freedreno/a6xx: few register updatesRob Clark2020-02-181-2/+65
* freedreno/a6xx: document some unknown bitsJonathan Marek2020-02-141-1/+9
* freedreno/a6xx: use single format enumJonathan Marek2020-02-121-229/+136
* freedreno: Document CP_UNK_A6XX_55Connor Abbott2020-01-241-12/+0
* freedreno: Add some missing a6xx address declarations.Eric Anholt2020-01-231-0/+5
* freedreno/registers: document vertex/instance id offset bitsJonathan Marek2019-12-191-1/+6
* freedreno/a6xx: RB6_R8G8B8 is actually 32 bit RGBXKristian H. Kristensen2019-12-191-1/+1
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-17 21:48:16 +0000