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path: root/src/freedreno/ir3/disasm-a3xx.c
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* freedreno/ir3: add debug code to print conflicting half-regsRob Clark2020-06-111-0/+7
* freedreno/ir3: Avoid {0} initializer for struct reginfoKristian H. Kristensen2020-05-261-3/+4
* freedreno: Set the immediate flag in a4/a5xx resinfos.Eric Anholt2020-05-261-8/+20
* freedreno: Fix printing of unused src in disasm of cat6 RESINFO.Eric Anholt2020-05-261-5/+9
* freedreno/ir3: Define the bindful uniform/nonuniform desc modes for cat6 a6xx.Eric Anholt2020-05-041-7/+19
* freedreno/ir3: Sync some new changes from envytools.Eric Anholt2020-05-041-13/+52
* freedreno/ir3: Add support for disasm of cat2 float32 immediates.Eric Anholt2020-04-271-6/+30
* freedreno/ir3: Refactor out print_reg_src().Eric Anholt2020-04-271-10/+6
* freedreno/ir3: Convert remaining disasm src prints to reginfo.Eric Anholt2020-04-271-60/+92
* freedreno/ir3: Print a space after nop counts, like qcom's disasm.Eric Anholt2020-04-271-1/+1
* freedreno/ir3: Fix the disasm of half-float STG dests.Eric Anholt2020-04-271-1/+1
* freedreno/ir3: fix 16-bit ssbo accessJonathan Marek2020-04-241-1/+2
* ir3: Fix LDC offset unitsConnor Abbott2020-04-151-0/+2
* freedreno/ir3: spiff out disasm a bitRob Clark2020-04-131-5/+17
* ir3: Add bindless instruction encodingConnor Abbott2020-04-091-48/+139
* freedreno/ir3: fix printing half constant registers.Hyunjun Ko2020-02-071-3/+4
* freedreno/ir3: rename instructionsRob Clark2020-01-151-3/+4
* freedreno/ir3: sync disasm changes from envytoolsRob Clark2019-11-091-23/+86
* freedreno/ir3: Add new synchronization opcodesKristian H. Kristensen2019-11-071-0/+3
* freedreno/a6xx: Add register offset for STG/LDGKristian H. Kristensen2019-11-071-2/+31
* freedreno/ir3: rename mul.s/mul.uRob Clark2019-10-181-2/+2
* freedreno/ir3: fix rgetpos decodingRob Clark2019-04-251-1/+1
* freedreno/ir3: fix sam.s2en decodingRob Clark2019-03-211-3/+5
* freedreno/ir3 better cat6 encoding detectionRob Clark2019-03-211-4/+1
* freedreno/ir3: sync instr/disasm and add ldib encodingRob Clark2019-02-201-10/+17
* freedreno/ir3: sync instr/disasmRob Clark2018-12-071-16/+78
* freedreno: move ir3 to common locationRob Clark2018-11-271-0/+1038
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