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* radv/android: Use buffer metadata to determine scanout compat.Bas Nieuwenhuizen2018-12-041-0/+53
* amd/addrlib: update Mesa's copy of addrlibNicolai Hähnle2018-11-292-2/+1
* radv: Align large buffers to the fragment size.Bas Nieuwenhuizen2018-11-271-1/+5
* radv/winsys: remove the max IBs per submit limit for the sysmem pathSamuel Pitoiset2018-11-191-17/+29
* radv/winsys: remove the max IBs per submit limit for the fallback pathSamuel Pitoiset2018-11-191-48/+55
* radv/winsys: do not assign last submission when chained path failedSamuel Pitoiset2018-10-311-1/+4
* radv/winsys: fix buffer deletion in the sysmem pathSamuel Pitoiset2018-10-311-2/+3
* radv/winsys: cleanup the chained submission pathSamuel Pitoiset2018-10-311-11/+17
* radv/winsys: remove unused surface_best()Samuel Pitoiset2018-10-311-7/+0
* radv/winsys: fix creating the BO list for virtual buffersSamuel Pitoiset2018-08-171-1/+1
* radv/winsys: use alloca() for semaphore dependenciesSamuel Pitoiset2018-07-171-6/+2
* radv: get rid of buffer object prioritiesSamuel Pitoiset2018-07-121-45/+14
* radv: winsys/amdgpu: include missing pthread.h headerMauro Rossi2018-07-071-0/+1
* radv/winsys: make use of radeon_emit()Samuel Pitoiset2018-07-051-11/+12
* amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbufMarek Olšák2018-06-191-33/+33
* radv/winsys: allow to allocate BOs in the 32-bit addr spaceSamuel Pitoiset2018-05-221-1/+2
* radv/winsys: request high addressSamuel Pitoiset2018-05-221-4/+6
* amd: remove support for LLVM 4.0Marek Olšák2018-05-171-7/+0
* radv/winsys: fix leaking resources from bo's imported by fdAndres Rodriguez2018-04-301-0/+1
* radv/winsys: allow to submit up to 4 IBs for chips without chainingSamuel Pitoiset2018-04-201-50/+168
* radv/winsys: allow local BOs on APUsSamuel Pitoiset2018-04-201-1/+2
* radv: Keep a global BO list for VkMemory.Bas Nieuwenhuizen2018-04-181-7/+39
* mesa: include mtypes.h lessMarek Olšák2018-04-122-0/+4
* radv: Use the syncobj wait ioctl to wait on fences if possible.Bas Nieuwenhuizen2018-03-011-4/+4
* radv: Implement more efficient !waitAll fence waiting.Bas Nieuwenhuizen2018-03-011-0/+34
* radv: implement VK_EXT_external_memory_hostFredrik Höglund2018-02-081-0/+49
* radv/ws: get rid of useless return valueDave Airlie2018-01-181-3/+2
* radv/winsys: make IBs read-only for the GPUSamuel Pitoiset2018-01-081-6/+11
* radv/winsys: add RADEON_FLAG_READ_ONLYSamuel Pitoiset2018-01-081-1/+3
* radv/winsys: rework radv_amdgpu_bo_va_op()Samuel Pitoiset2018-01-081-17/+23
* radv: move local bos usage to a perftest flag.Dave Airlie2017-12-283-1/+3
* radv: Use a sort for rebuilding the sparse buffer bo list.Bas Nieuwenhuizen2017-12-191-21/+24
* radv/amdgpu: wrap sync fd import/export.Bas Nieuwenhuizen2017-12-181-0/+21
* radv: Add syncobj signal/reset/wait to winsys.Bas Nieuwenhuizen2017-12-181-0/+40
* radv/winsys: implement query_value()Samuel Pitoiset2017-12-081-0/+56
* radv/winsys: improve error messages when the buffer list creation failedSamuel Pitoiset2017-11-241-3/+6
* radv/winsys: do not try to create a BO list with 0 buffersSamuel Pitoiset2017-11-241-3/+9
* amd/addrlib: update to latest versionMarek Olšák2017-11-082-2/+0
* radv: move is_local up to the winsys level.Dave Airlie2017-11-063-3/+2
* radv: add support for local bos. (v3)Dave Airlie2017-10-263-8/+29
* radv: disable implicit sync for radv allocated bos v3Andres Rodriguez2017-10-211-0/+2
* radv: Implement VK_EXT_global_priorityAndres Rodriguez2017-10-211-4/+22
* radv: Only set the MTYPE flags on GFX9+.Bas Nieuwenhuizen2017-10-111-1/+1
* amd: move r600d_common.h into r600gMarek Olšák2017-10-091-1/+0
* radv: Don't use a virtual function for getting the buffer virtual address.Bas Nieuwenhuizen2017-09-203-22/+15
* radv: add get_chip_name() callbackSamuel Pitoiset2017-09-151-0/+8
* radv/winsys: add a read_registers() callbackSamuel Pitoiset2017-09-141-0/+11
* radv: add debug flags to zero vram allocations.Dave Airlie2017-09-123-0/+5
* radv/winsys: fix flags vs va_flags thinko.Dave Airlie2017-09-081-1/+1
* radv/gfx9: allocate events from uncached VA spaceDave Airlie2017-09-071-1/+5
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