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path: root/src/amd/vulkan/radv_pipeline.c
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* radv: Fix up 2_10_10_10 alpha sign.Bas Nieuwenhuizen2018-05-151-2/+27
* radv: Translate logic ops.Bas Nieuwenhuizen2018-05-151-2/+43
* radv: Always lower indirect derefs after nir_lower_global_vars_to_local.Bas Nieuwenhuizen2018-02-281-2/+9
* radv: move spi_baryc_cntl to pipelineDave Airlie2018-01-261-0/+3
* radv: fix sample_mask_in loading. (v3.1)Dave Airlie2018-01-261-5/+24
* radv: emit pa_sc_mode_cntl_0 with multisample state.Bas Nieuwenhuizen2018-01-191-1/+2
* radv: Use correct bindings for inputRate in key generation.Bas Nieuwenhuizen2018-01-191-1/+7
* Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"Samuel Pitoiset2018-01-151-0/+2
* ac/shader: gather If TES reads TESSINNER or TESSOUTERSamuel Pitoiset2018-01-151-2/+0
* radv: Implement VK_EXT_discard_rectangles.Bas Nieuwenhuizen2018-01-101-0/+35
* radv: Add mapping between dynamic state mask and external enum.Bas Nieuwenhuizen2018-01-101-11/+38
* amd/common: scan if gl_PrimitiveID is used before translating to LLVMSamuel Pitoiset2018-01-041-3/+3
* radv: Implement binning on GFX9.Bas Nieuwenhuizen2017-12-311-0/+325
* radv/gfx9: fix primitive topology when adjacency is usedSamuel Pitoiset2017-12-211-1/+1
* radv: add assertions to make sure pipeline layout objects are validSamuel Pitoiset2017-12-191-0/+2
* amd/common: add ac_vgt_gs_mode() helperSamuel Pitoiset2017-12-181-26/+6
* amd/common: add ac_get_cb_shader_mask() helperSamuel Pitoiset2017-12-181-33/+1
* radv: port merge tess info from anvDave Airlie2017-12-181-0/+40
* radv: export SampleMask from pixel shaders at full rateSamuel Pitoiset2017-12-141-5/+6
* radv: enable nir varying array splittingTimothy Arceri2017-12-041-0/+3
* radv: enable nir component packingTimothy Arceri2017-12-041-0/+6
* radv: do not dump meta shaders with RADV_DEBUG=shadersSamuel Pitoiset2017-12-011-4/+1
* radv: drop radv_cmd_dirty_mask_t typedefSamuel Pitoiset2017-11-151-1/+1
* radv: use vk_zalloc instead of vk_alloc+memsetSamuel Pitoiset2017-11-131-6/+4
* radv: use vk_error() everywhere an error is returnedSamuel Pitoiset2017-11-131-1/+1
* radv: emit esgs ring size in one place.Dave Airlie2017-11-131-0/+1
* radv: move calculating vs out info regs into pipeline.Dave Airlie2017-11-131-3/+18
* radv: pre-calculate user_data_0 registers and store in pipelineDave Airlie2017-11-061-2/+47
* radv: Implement VK_AMD_shader_infoAlex Smith2017-10-291-1/+1
* radv: store the dynamic state mask into radv_dynamic_stateSamuel Pitoiset2017-10-261-1/+1
* radv: Compute ac keys from pipeline key.Bas Nieuwenhuizen2017-10-261-72/+41
* radv: Add single pipeline cache key.Bas Nieuwenhuizen2017-10-261-3/+41
* radv: Don't compute as_ls/as_es before hashing.Bas Nieuwenhuizen2017-10-261-14/+12
* radv: print NIR before LLVM IR and disassemblySamuel Pitoiset2017-10-251-7/+10
* radv: enable lower to scalar nir passTimothy Arceri2017-10-251-0/+24
* radv: move nir print after linking is doneTimothy Arceri2017-10-241-2/+7
* radv: clone meta shaders before linkingTimothy Arceri2017-10-241-1/+8
* radv/ac/nir: only emit tess factors to storage if tes reads themDave Airlie2017-10-231-0/+1
* radv: Don't compile shaders when they are cached already.Bas Nieuwenhuizen2017-10-211-19/+23
* radv: Don't check for max GL GS invocations.Bas Nieuwenhuizen2017-10-211-2/+0
* radv: calculate and emit GFX9 GS registers to pipeline state.Bas Nieuwenhuizen2017-10-201-2/+124
* radv: fixup tess eval shader when combined.Dave Airlie2017-10-201-6/+18
* radv: Set VGT_GS_MODE properly for gfx9Bas Nieuwenhuizen2017-10-201-4/+7
* radv: ensure correct outinfo is picked.Dave Airlie2017-10-201-13/+14
* radv: stop redundant setting of active_stagesTimothy Arceri2017-10-201-2/+0
* radv: Remove remaining hard coded references to VS.Bas Nieuwenhuizen2017-10-191-2/+12
* radv: Update GFX9 user data regs for GS/tess.Bas Nieuwenhuizen2017-10-191-1/+1
* radv: Add code to compile merged shaders.Bas Nieuwenhuizen2017-10-191-4/+25
* radv: Set active_stages after getting cached shadersAlex Smith2017-10-181-1/+6
* radv: Don't free NIR shaders if tracingAlex Smith2017-10-181-1/+1
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