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* ac/nir: Use lower_vote_eq_to_ballot instead of ac_nir_lower_subgroupsJason Ekstrand2018-03-131-2/+0
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: rename radeon_llvm_reg_index_soa() to ac_llvm_reg_index_soa()Samuel Pitoiset2018-03-131-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: remove some unnecessary includes and declarationsSamuel Pitoiset2018-03-131-5/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move ac_nir_compiler_options and friends to radv folderSamuel Pitoiset2018-03-131-72/+0
| | | | | | | Also replace ac_ by radv_. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: move ac_shader_info to radv folderSamuel Pitoiset2018-03-131-1/+0
| | | | | | | This is RADV specific code. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move ac_shader_variant_info and friends to radv folderSamuel Pitoiset2018-03-131-97/+0
| | | | | | | Also replace ac_ by radv_. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move all RADV related code to radv_nir_to_llvm.cSamuel Pitoiset2018-03-131-17/+0
| | | | | | | | Now the "ac/nir" prefix will really be the shared code between RadeonSI and RADV, that might avoid confusions in the future. Signed-off-by: Samuel Pitoiset <[email protected]> Acked-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: make emit_barrier() non-staticSamuel Pitoiset2018-03-131-0/+2
| | | | | | | Required in order to move all RADV specific code outside of ac/nir. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: move radeon_llvm_reg_index_soa() to ac_nir_to_llvm.hSamuel Pitoiset2018-03-131-0/+5
| | | | | | | Required in order to move all RADV specific code outside of ac/nir. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: make handle_shader_output_decl() non-staticSamuel Pitoiset2018-03-131-0/+8
| | | | | | | Required in order to move all RADV specific code outside of ac/nir. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: Add vote_ieq/vote_feq lowering pass.Bas Nieuwenhuizen2018-03-071-0/+2
| | | | | | | | | | | | The old vote_eq implementation supported only booleans, but now we have to support arbitrary values, so use the read_first_invocation intrinsic + ballot. I took this as an opportunity to figure out how easy it was to do this in nir instead of in the nir_to_llvm pass, and it actually turned out pretty okay IMO. Only creating the pass is some extra code. Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: count the scratch private memory sizeSamuel Pitoiset2018-03-061-0/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac/radv: move lower_indirect_derefs() to ac_nir_to_llvm.cTimothy Arceri2018-03-051-0/+2
| | | | | | | Until llvm handles indirects better we will need to use these workarounds in the radeonsi backend also. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/shader: move scanning some info about input PS declarationsSamuel Pitoiset2018-02-281-3/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* ac: remove nir_to_llvm_context from ac_nir_translate()Samuel Pitoiset2018-02-141-2/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/shader: scan info about output PS declarationsSamuel Pitoiset2018-02-081-3/+0
| | | | | | | | NIR->LLVM should only be a translation pass, and all scan stuff should be done before. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir: remove set but unused export_maskSamuel Pitoiset2018-02-081-1/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac/nir_to_llvm: move some interp defines to the headerTimothy Arceri2018-01-311-0/+5
| | | | | | These will be used in the following patch. Reviewed-by: Marek Olšák <[email protected]>
* ac/shader: scan if fragment shaders write memorySamuel Pitoiset2018-01-261-1/+0
| | | | | | | It's better to do that in ac_shader_info. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix sample_mask_in loading. (v3.1)Dave Airlie2018-01-241-0/+2
| | | | | | | | | | | | | | This is ported from radeonsi and fixes: dEQP-VK.pipeline.multisample_shader_builtin.sample_mask.bit_* v2: don't call this path for radeonsi, it does it in the epilog. use the radeonsi code path. v3: handle NULL pCreateInfo->pMultisampleState properly (Samuel) v3.1: set ps_iter_samples default to 1 (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Fixes: bdcbe7c76 (radv: add sample mask input support) Signed-off-by: Dave Airlie <[email protected]>
* radv: add an option that allows to dump pre-optimization irSamuel Pitoiset2018-01-221-0/+1
| | | | | | | With RADV_DEBUG=preoptir. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* Revert "ac/shader: gather If TES reads TESSINNER or TESSOUTER"Samuel Pitoiset2018-01-151-0/+1
| | | | | | | | | | | | | This can't work for two reasons: - TESSINNER/TESSOUTER are shader input values, so never translated to the intrinsic ops - the shader info pass scans the current stage but we want to know in TCS, if TES reads the tess factors. This fixes 6 regressions related to deqp-vk/tessellation/shader_input_output/tess_level_{inner,outer}_XXX_tes This reverts commit 5ba1a61648e2dea96f621a5886ad8b937a471ab4.
* ac/shader: gather If TES reads TESSINNER or TESSOUTERSamuel Pitoiset2018-01-151-1/+0
| | | | | | | This shouldn't be scanned in the pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* ac: remove ac_shader_variant_info::fs::output_maskSamuel Pitoiset2018-01-151-1/+0
| | | | | | | Unused. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* amd/common: determine the ES type (VS or TES) for the GS on GFX9Samuel Pitoiset2018-01-101-0/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: scan if gl_PrimitiveID is used before translating to LLVMSamuel Pitoiset2018-01-041-3/+0
| | | | | | | | | It makes more sense to move all scan stuff in the same place. Also, we don't really need to duplicate the uses_primid field for each stages. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac/nir: Only clamp shadow reference on radeonsi.Bas Nieuwenhuizen2017-10-231-0/+1
| | | | | | | | | | | | | | | | | | Vulkan CTS does not expect the value to be clamped (at least for D32), and it makes a differences even though depth is in [0,1], due to strict inequalities. I couldn't find anything in the Vulkan spec about this, but the test seemed to be copied from GL tests and the GL spec only specifies clamping for fixed point formats. Hence I expect radeonsi to run into this at some point as well, but given that they still have a usecase with the Z16->Z32 promotion, I'll leave that for someone else to clean up. This at least fixes radv dEQP-VK.texture.shadow.* on VI. Fixes: 0f9e32519bb 'ac/nir: clamp shadow texture comparison value on VI' Reviewed-by: Dave Airlie <[email protected]>
* radv/ac/nir: only emit tess factors to storage if tes reads themDave Airlie2017-10-231-0/+1
| | | | | | | | | | Otherwise we just need to write them to the tf ring. this seems to improve the tessellation demo on Bonarie ~2190->~2230 fps Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add code to compile merged shaders.Bas Nieuwenhuizen2017-10-191-0/+1
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Expand user SGPR descriptions a bit.Bas Nieuwenhuizen2017-10-191-3/+3
| | | | | | To prevent VS/TCS collisions in merged shaders. Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Allow ac_shader_variant_info to contain info about multiple stages.Bas Nieuwenhuizen2017-10-191-1/+1
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Change interface to allow multiple source shaders.Bas Nieuwenhuizen2017-10-191-1/+2
| | | | Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Add shader support for multiviews.Bas Nieuwenhuizen2017-08-241-1/+3
| | | | | | | | | It uses an user SGPR to pass the view index to the shaders, except for the fragment shader where we use layer=view (which comes in handy when we want to do the NV ext that allows us to execute pre-FS stages once instead of per view). Reviewed-by: Dave Airlie <[email protected]>
* ac/nir: Make shader key a struct.Bas Nieuwenhuizen2017-08-241-6/+8
| | | | | | | Some bits can be passed to almost every shader, and I don't like adding 5 variables. Reviewed-by: Dave Airlie <[email protected]>
* radv: Implement bc optimize.Bas Nieuwenhuizen2017-08-241-0/+1
| | | | | | | | Seems like we actually enabled it already, but did not implement the shader part. With this patch we do. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: handle 10-bit format clamping workaround.Dave Airlie2017-08-011-0/+1
| | | | | | | | | | | | | | | This fixes: dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.* for a2r10g10b10 formats as destination on SI/CIK hardware. This adds support to the meta program for emitting 10-bit outputs, and adds 10-bit support to the fragment shader key. It also only does the int8/10 on SI/CIK. Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ac/nir,radv: move force_persample to ac_shader_info::force_persampleNicolai Hähnle2017-07-311-1/+0
| | | | | | | Avoid accessing radv-specific structures during the meat of NIR-to-LLVM translation. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: translate NIR to LLVMNicolai Hähnle2017-07-311-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/nir: begin splitting off ac_nir_contextNicolai Hähnle2017-07-311-0/+6
| | | | | | | | | | | | | The eventual goal is to hide all radv-specific details behind ac_nir_context::abi, so that the NIR->LLVM code can be re-used by radeonsi. During development, we live with a partial split, where some of the NIR->LLVM code still relies on linking back to the nir_to_llvm_context (which should ultimately be renamed to reflect that it's radv-specific). The idea is to get rid of these backlinks over time. Reviewed-by: Marek Olšák <[email protected]>
* radv: handle primitive id input into fragment shader with no geom shaderDave Airlie2017-06-261-0/+3
| | | | | | | | | | Fixes: dEQP-VK.pipeline.framebuffer_attachment.no_attachments dEQP-VK.pipeline.framebuffer_attachment.no_attachments_ms Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: set prim_id for geometry shadersDave Airlie2017-06-261-0/+1
| | | | | | | | Noticed in passing. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: eliminate unused vertex shader outputs. (v2)Dave Airlie2017-04-271-13/+1
| | | | | | | | | | | This is ported from radeonsi, and I can see at least one Talos shader drops an export due to this, and saves some VGPR usage. v2: use shared code. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: overhaul vs output/ps input routingDave Airlie2017-04-251-2/+13
| | | | | | | | In order to cleanly eliminate exports rewrite the code first to mirror how radeonsi works for now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: add support for indirect access of descriptor sets.Dave Airlie2017-04-191-2/+3
| | | | | | | | | | | | | | | | | | | We want to expose more descriptor sets to the applications, but currently we have a 1:1 mapping between shader descriptor sets and 2 user sgprs, limiting us to 4 per stage. This commit check if we don't have enough user sgprs for the number of bound sets for this shader, we can ask for them to be indirected. Two sgprs are then used to point to a buffer or 64-bit pointers to the number of allocated descriptor sets. All shaders point to the same buffer. We can use some user sgprs to inline one or two descriptor sets in future, but until we have a workload that needs this I don't think we should spend too much time on it. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: add initial pre-pass for shader info gatheringDave Airlie2017-04-191-2/+2
| | | | | | | | | | | | There is some radv specific info we need to gather from shaders before we get into converting nir->llvm, so we can make better decisions especially around user sgpr allocation. This is just an initial placeholder to gather if sample positions are required in the frag shader. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: overhaul fragment shader sample positions.Dave Airlie2017-04-041-1/+3
| | | | | | | | | | | | | | | | | | The current code was broken, and I decided to redesign it instead. This puts the sample positions for all samples into the queue constant descriptor buffer after all the spill/ring descriptors. It then uses a single offset register to point how far into the samples the samples for num_samples are. This saves one user sgpr and means we only generate the sample position data in the rare single case where we need it currently. This doesn't fix the failing CTS tests without the followup fix. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: setup tess rings on compiler side.Dave Airlie2017-04-011-0/+2
| | | | | | | | This just sets up the necessary pointers on the compiler side for the rings needed for tessellation. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/ac: add tess changes to shader keys/infoDave Airlie2017-04-011-0/+40
| | | | | | | | This adds the tess pieces for shader keys and shader info, it adds the necessary bits to the vertex key/info as well. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: use defines for ring descriptor offsets.Dave Airlie2017-04-011-0/+7
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: rework vertex/export shader output handlingDave Airlie2017-03-281-11/+19
| | | | | | | | | In order to faciliate adding tess support, split the vs/es output info into a separate block, so we make it easier to have the tess shaders export the same info. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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