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* anv: Make use of devinfo has_aux_map fieldJordan Justen2020-06-223-13/+16
| | | | | | | | | Reworks: * Use device rather than physical_device for info. (Lionel) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5572>
* iris: Make use of devinfo has_aux_map fieldJordan Justen2020-06-221-1/+1
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5572>
* gitlab-ci: drop gettext from the build imagesEric Engestrom2020-06-224-6/+3
| | | | | | Suggested-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* util: rename xmlpool.h to driconf.hEric Engestrom2020-06-2227-29/+29
| | | | | | | To make it clearer what it is and does. Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* driconf: drop now unused translation facilityEric Engestrom2020-06-2239-842/+439
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* driconf: drop 9% swedish translationEric Engestrom2020-06-224-287/+3
| | | | | | | | Only 7 of the 72 strings are translated, and there doesn't seem to be any effort to keep it updated. Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* driconf: drop 8% dutch translationEric Engestrom2020-06-224-280/+3
| | | | | | | | Only 6 of the 72 strings are translated, and there doesn't seem to be any effort to keep it updated. Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* driconf: drop 6% french translationEric Engestrom2020-06-224-275/+3
| | | | | | | | Only 4 of the 72 strings are translated, and there doesn't seem to be any effort to keep it updated. Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* driconf: drop 26% spanish translationEric Engestrom2020-06-224-280/+3
| | | | | | | | Only 19 of the 72 strings are translated, and there doesn't seem to be any effort to keep it updated. Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* driconf: drop 15% german translationEric Engestrom2020-06-224-282/+3
| | | | | | | | Only 11 of the 72 strings are translated, and there doesn't seem to be any effort to keep it updated. Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* driconf: drop 28% catalan translationEric Engestrom2020-06-223-293/+2
| | | | | | | | Only 20 of the 72 strings are translated, and there doesn't seem to be any effort to keep it updated. Signed-off-by: Eric Engestrom <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5440>
* zink: use correct define value for reserved slot count in ntvMike Blumenkrantz2020-06-221-1/+1
| | | | | | | this is zero-indexed, so we need to include the zero index in the count Reviewed-by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5592>
* intel/dev: Add device info for DG1Jordan Justen2020-06-222-0/+14
| | | | | | | | | | | | | Reworks: * Anuj: Set is_dg1 * Anuj: Add dg1 to gen_device_name_to_pci_device_id * Anuj: Update simulator id * Rafael: has_llc = false Signed-off-by: Jordan Justen <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* anv/dg1: Don't use SET_TILING kernel uapi.Rafael Antognolli2020-06-222-4/+20
| | | | | | | It is not available on discrete platforms anymore. Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* iris/bufmgr: Do not use map_gtt or use set/get_tiling on DG1Rafael Antognolli2020-06-223-11/+37
| | | | | | | | | | | | | | | | | | | | | We are starting to see platforms that don't support the get/set tiling uAPI. (For example, DG1.) Additionally on DG1 we shouldn't be using the map_gtt anymore. Let's add some asserts and make sure we don't take those paths accidentally. Rework: * Jordan: Only apply for DG1, not all gen12 * Rafael: Use has_tiling_uapi * Jordan: Copy has_tiling_uapi from devinfo * Jordan: merge in "iris: Rework iris_bo_import_dmabuf() a little." * Jordan: Continue to call get/set_tiling on modifier path Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/devinfo: Add function to check for DRM_I915_GEM_GET_TILING.Rafael Antognolli2020-06-222-0/+29
| | | | | | | | | Future (discrete) platforms won't have support for get/set tiling. This function allows our drivers to query for that, by simply trying to get the tiling from a dummy buffer. Reviewed-by: Jordan Justen <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/l3: Return the URB size from devinfo for DG1Rafael Antognolli2020-06-221-0/+4
| | | | | | | | | We don't have any URB size set in the L3 config, since it's a fixed value now. So just return the value that we know from gen_device_info. Reviewed-by: Jordan Justen <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/isl: Update mocs for DG1Rafael Antognolli2020-06-221-5/+14
| | | | | | Reviewed-by: Jordan Justen <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/l3: Add DG1 L3 configurationAnuj Phogat2020-06-221-1/+12
| | | | | | | | | | | Reworks: * Jordan: Make DG1 L3 config table empty Signed-off-by: Anuj Phogat <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* anv: Set L3 full way allocation at context init if L3 cfg is NULLJordan Justen2020-06-222-1/+15
| | | | | | | | | | | | | | If the platform's default L3 config is NULL, then it now gets initialized only at context init time, and cmd_buffer_config_l3 will always return immediately. Rework: * Remove unneeded check on !cfg in cmd_buffer_config_l3 (Jason) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* iris/l3: Enable L3 full way allocation when L3 config is NULLJordan Justen2020-06-221-4/+11
| | | | | | | | | | Reworks: * Jordan: Check for cfg == NULL rather than is_dg1 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/l3: Allow platforms to have no l3 configurationsJordan Justen2020-06-221-4/+10
| | | | | | | | | | | | On some gen12 platforms we will use the L3FullWayAllocationEnable and never reconfigure the L3 setup. Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/l3: Don't rely on cfg entry URB size being 0 as a sentinalJordan Justen2020-06-221-20/+32
| | | | | | | | | An example entry with URB size being 0 is in the cnl list. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* intel/devinfo: Add is_dg1 to device infoAnuj Phogat2020-06-221-0/+1
| | | | | | | Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
* turnip: Enable tessellationShader physical device featureBrian Ho2020-06-221-1/+1
| | | | Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* ir3: Unconditionally enable MERGEDREGS on a6xxBrian Ho2020-06-221-20/+1
| | | | | | | | | | | As per discussion on !5059, we don't see any particular reason as to why MERGEDREGS should be disabled on HS/DS/GS, and none of the dEQP tests (both VK and GL) fail when MERGEDREGS is enabled. In fact, some of the VK dEQP tests fail when MERGEDREGS is disabled (e.g. tests with shaders that employ a0.x). As a result, let's just enable MERGEDREGS unconditionally on a6xx. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* turnip: Force sysmem for tessellationBrian Ho2020-06-222-0/+9
| | | | | | | | Tessellation is incompatible with HW binning (dEQP tests fail when we set forcebin), so force sysmem when we finish recording a command buffer that uses a tess pipeline. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* turnip: Support tess for drawsBrian Ho2020-06-224-7/+45
| | | | | | | | | This commit adds tessellation support for draws. We store the IR3 patch type in tu_pipeline so we can use it in tu_emit_draw_*. We then convert the IR3 patch type to the native adreno patch type and set the appropriate reg values. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* turnip: Emit HS/DS user consts as draw statesBrian Ho2020-06-222-1/+11
| | | | | | Just like VS/GS/FS. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* turnip: Update VFD_CONTROL with tess system valuesBrian Ho2020-06-223-12/+136
| | | | | | Support for TessCoord, PatchID, TCSHeader. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* turnip: Allocate tess BOs as a function of draw sizeBrian Ho2020-06-223-18/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To store tess outputs, the HS stg's into two buffers, one for per-vertex/per-patch output variables (tess_param) and one for TessLevelInner/Outer (tess_factor). The addresses of these buffers are uploaded as consts to the HS/DS and the tess_factor iova is written to REG_A6XX_PC_TESSFACTOR_ADDR. While the sizes of these buffers are a function of vetex count and patch count, allocation is relatively straightforward on freedreno- just keep track of the max required buffer size for the entire batch and allocate before batch submit. In Vulkan, however, a given pipeline can be bound multiple times across any number of command buffers, each drawing with a different number of vertices. One solution is to track the max buffer size for the entire command buffer (similar to fd_batch) and on vkEndCommandBuffer, allocate appropriately sized tess BOs. Since the tess BOs addresses are emitted as part of the pipeline state setup (e.g. PKT4 to REG_A6XX_PC_TESSFACTOR_ADDR), we need to create a new state group independent of a specific pipeline and parameterize its IB with the command buffer specific tess BO iovas. Without a larger refactor, the simplest way to do this is just to emit per-draw call consts and leverage scratch_bo to re-use buffers. This way we won't have to store and rewrite earlier packets in the command stream on vkEndCommandBuffer. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* turnip: Parse tess state and support PATCH primtypeBrian Ho2020-06-222-1/+18
| | | | | | | This commit adds support for VK_PRIMITIVE_TOPOLOGY_PATCH_LIST primitive topologies. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* turnip: Offset by component when lowering gl_TessLevel*Brian Ho2020-06-221-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | lower_tess_ctrl_block assumes that the gl_TessLevel* intrinsic_store_outputs have already been collapsed into a single instruction before the tess lowering step: store_output ... /* base=0 */ /* wrmask=xyzw */ /* component=0 */ store_output ... /* base=1 */ /* wrmask=xy */ /* component=0 */ While this is true in fd because of st_nir_vectorize_io, we don't do the same lowering in turnip so each tess level component still has its own store instruction: store_output ... /* base=0 */ /* wrmask=x */ /* component=0 */ store_output ... /* base=0 */ /* wrmask=x */ /* component=1 */ store_output ... /* base=0 */ /* wrmask=x */ /* component=2 */ store_output ... /* base=0 */ /* wrmask=x */ /* component=3 */ store_output ... /* base=1 */ /* wrmask=x */ /* component=0 */ store_output ... /* base=1 */ /* wrmask=x */ /* component=1 */ This commit adds a component offset to the tess control lowering. An alternative is to also perform nir_lower_io_to_vector in turnip, but ir3 seems to generate the same assembly either way and it's nice to not have a lowering prereq before tess lowering. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* turnip: Lower shaders for tessellationBrian Ho2020-06-222-2/+37
| | | | | | | | | To enable lowering of tess-related shaders, this commit sets the tessellation primitive field of the ir3_shader_key. In addition, this commit sets various tessellation flags for spirv_to_nir configuration. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* nir: Add an option for lowering TessLevelInner/Outer to vecsBrian Ho2020-06-222-0/+30
| | | | | | | | | | | | The GLSL to NIR compiler supports the LowerTessLevel flag to convert gl_TessLevelInner/Outer from their GLSL declarations as arrays of floats to vec4/vec2s to better match how they are represented in hardware. This commit adds the similar support to the SPIR-V to NIR compiler so turnip can use the same IR3/NIR tess lowering passes as freedreno. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* nir: Support sysval tess levels in SPIR-V to NIRBrian Ho2020-06-222-2/+19
| | | | | | | | | | This commit adds a tess_levels_are_sysvals flag to spirv_to_nir_options similar to GLSLTessLevelsAsInputs in the GLSL to NIR compiler options. This will be used by turnip as the tess IR3 lowering pass (ir3_nir_lower_tess) operates on TessLevelInner and TessLevelOuter in the DS as sysvals. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
* v3d: Disable PIPE_CAP_PRIMITIVE_RESTARTNeil Roberts2020-06-222-2/+1
| | | | | | | | | | | | | The hardware can only support the PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX subset. This will make it stop advertising the NV_primitive_restart extension without breaking GLES 3.0 support. v2: Update features.txt Reviewed-by: Eric Anholt <[email protected]> (v1) Reviewed by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>
* mesa: Add PrimitiveRestartFixedIndex to gl_constantsNeil Roberts2020-06-224-2/+16
| | | | | | | | | | | | This is a fine-grained subset of the NV_primitive_restart extension that only uses the fixed indices provided by GLES 3.0. There’s no public extension to advertise this behaviour so the bool is added to gl_constants instead of gl_extensions. Reviewed-by: Eric Anholt <[email protected]> Reviewed by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>
* gallium: Add pipe cap for primitive restart with fixed indexNeil Roberts2020-06-2220-0/+25
| | | | | | | | | | | | | | | | | | | | Adds PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX which is a subset of the primitive restart cap for when the hardware can only support the fixed indices specified in GLES. The switch statements were automatically modified with this command: find \( \( -name \*.cpp -o -name \*.c \) \! -type l \) \ -exec sed -i -r \ 's/^(\s*case\s+PIPE_CAP_PRIMITIVE_RESTART)\s*:.*$/\0\n\1_FIXED_INDEX:/' \ {} \; v2: Add a note in screen.rst Reviewed-by: Eric Anholt <[email protected]> (v1) Reviewed by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5559>
* nv50/ir/ra: fix memory corruption when spillingKarol Herbst2020-06-221-22/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When doing RA we end up with adding ValueDef references to Values across all over the shader. This is all fine until we remove the Instruction defining those Values, which happens when spilling values. Instead of manipulating the values directly we should just track all merged in defs in a seperate structure and remove stale references when an instruction gets deleted in the spiller. fixes following libasan report: ================================================================= ==612087==ERROR: AddressSanitizer: heap-use-after-free on address 0x6150003ea380 at pc 0x7f1d12142fe9 bp 0x7fffca6fd120 sp 0x7fffca6fd110 READ of size 8 at 0x6150003ea380 thread T0 #0 0x7f1d12142fe8 in nv50_ir::ValueDef::get() const ../src/gallium/drivers/nouveau/codegen/nv50_ir.h:648 #1 0x7f1d12143c02 in nv50_ir::Value::getUniqueInsn() const ../src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h:229 #2 0x7f1d1221530d in nv50_ir::RegAlloc::BuildIntervalsPass::addLiveRange(nv50_ir::Value*, nv50_ir::BasicBlock const*, int) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:333 #3 0x7f1d1221872e in nv50_ir::RegAlloc::BuildIntervalsPass::visit(nv50_ir::BasicBlock*) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:686 #4 0x7f1d1215676c in nv50_ir::Pass::doRun(nv50_ir::Function*, bool, bool) ../src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp:495 #5 0x7f1d121563ed in nv50_ir::Pass::run(nv50_ir::Function*, bool, bool) ../src/gallium/drivers/nouveau/codegen/nv50_ir_bb.cpp:477 #6 0x7f1d122262b8 in nv50_ir::RegAlloc::execFunc() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1910 #7 0x7f1d122256b0 in nv50_ir::RegAlloc::exec() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1849 #8 0x7f1d12226f1e in nv50_ir::Program::registerAllocation() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1970 #9 0x7f1d1214092a in nv50_ir_generate_code ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1275 #10 0x7f1d1227461b in nvc0_program_translate ../src/gallium/drivers/nouveau/nvc0/nvc0_program.c:634 #11 0x7f1d12294b21 in nvc0_sp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:620 #12 0x7f1d12294d90 in nvc0_fp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:661 #13 0x7f1d12ad4912 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1498 #14 0x7f1d12ad4cd5 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1525 #15 0x7f1d12ad8252 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:2053 #16 0x7f1d12c9c851 in st_program_string_notify ../src/mesa/state_tracker/st_cb_program.c:185 #17 0x7f1d12d17731 in st_link_tgsi ../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:7441 #18 0x7f1d12cabaf0 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_ir.cpp:175 #19 0x7f1d127c85ca in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3186 #20 0x7f1d1252a9f7 in link_program ../src/mesa/main/shaderapi.c:1285 #21 0x7f1d1252a9f7 in link_program_error ../src/mesa/main/shaderapi.c:1384 #22 0x7f1d1252deb3 in _mesa_LinkProgram ../src/mesa/main/shaderapi.c:1876 #23 0x403e13 in main._omp_fn.0 /home/kherbst/git/shader-db/run.c:926 #24 0x7f1d17b8b4b5 in GOMP_parallel (/lib64/libgomp.so.1+0x124b5) #25 0x4029e4 in main /home/kherbst/git/shader-db/run.c:765 #26 0x7f1d179b51a2 in __libc_start_main ../csu/libc-start.c:308 #27 0x402d1d in _start (/home/kherbst/git/shader-db/run+0x402d1d) 0x6150003ea380 is located 0 bytes inside of 504-byte region [0x6150003ea380,0x6150003ea578) freed by thread T0 here: #0 0x7f1d17e5d96f in operator delete(void*) (/usr/lib64/libasan.so.5.0.0+0x11096f) #1 0x7f1d1214ec0f in __gnu_cxx::new_allocator<nv50_ir::ValueDef>::deallocate(nv50_ir::ValueDef*, unsigned long) /usr/include/c++/9/ext/new_allocator.h:128 #2 0x7f1d1214dc00 in std::allocator_traits<std::allocator<nv50_ir::ValueDef> >::deallocate(std::allocator<nv50_ir::ValueDef>&, nv50_ir::ValueDef*, unsigned long) /usr/include/c++/9/bits/alloc_traits.h:470 #3 0x7f1d1214c5fb in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_deallocate_node(nv50_ir::ValueDef*) /usr/include/c++/9/bits/stl_deque.h:624 #4 0x7f1d121498c4 in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_destroy_nodes(nv50_ir::ValueDef**, nv50_ir::ValueDef**) /usr/include/c++/9/bits/stl_deque.h:758 #5 0x7f1d1214704d in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::~_Deque_base() /usr/include/c++/9/bits/stl_deque.h:680 #6 0x7f1d12145371 in std::deque<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::~deque() /usr/include/c++/9/bits/stl_deque.h:1069 #7 0x7f1d1213bc5b in nv50_ir::Instruction::~Instruction() ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:615 #8 0x7f1d1213fb2f in nv50_ir::Program::releaseInstruction(nv50_ir::Instruction*) ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1148 #9 0x7f1d122250fb in nv50_ir::SpillCodeInserter::run(std::__cxx11::list<std::pair<nv50_ir::Value*, nv50_ir::Value*>, std::allocator<std::pair<nv50_ir::Value*, nv50_ir::Value*> > > const&) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1830 #10 0x7f1d12221445 in nv50_ir::GCRA::allocateRegisters(nv50_ir::ArrayList&) ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1541 #11 0x7f1d122262e9 in nv50_ir::RegAlloc::execFunc() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1913 #12 0x7f1d122256b0 in nv50_ir::RegAlloc::exec() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1849 #13 0x7f1d12226f1e in nv50_ir::Program::registerAllocation() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp:1970 #14 0x7f1d1214092a in nv50_ir_generate_code ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1275 #15 0x7f1d1227461b in nvc0_program_translate ../src/gallium/drivers/nouveau/nvc0/nvc0_program.c:634 #16 0x7f1d12294b21 in nvc0_sp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:620 #17 0x7f1d12294d90 in nvc0_fp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:661 #18 0x7f1d12ad4912 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1498 #19 0x7f1d12ad4cd5 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1525 #20 0x7f1d12ad8252 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:2053 #21 0x7f1d12c9c851 in st_program_string_notify ../src/mesa/state_tracker/st_cb_program.c:185 #22 0x7f1d12d17731 in st_link_tgsi ../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:7441 #23 0x7f1d12cabaf0 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_ir.cpp:175 #24 0x7f1d127c85ca in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3186 #25 0x7f1d1252a9f7 in link_program ../src/mesa/main/shaderapi.c:1285 #26 0x7f1d1252a9f7 in link_program_error ../src/mesa/main/shaderapi.c:1384 #27 0x7f1d1252deb3 in _mesa_LinkProgram ../src/mesa/main/shaderapi.c:1876 #28 0x403e13 in main._omp_fn.0 /home/kherbst/git/shader-db/run.c:926 previously allocated by thread T0 here: #0 0x7f1d17e5c9d7 in operator new(unsigned long) (/usr/lib64/libasan.so.5.0.0+0x10f9d7) #1 0x7f1d1215046f in __gnu_cxx::new_allocator<nv50_ir::ValueDef>::allocate(unsigned long, void const*) /usr/include/c++/9/ext/new_allocator.h:114 #2 0x7f1d1214ebec in std::allocator_traits<std::allocator<nv50_ir::ValueDef> >::allocate(std::allocator<nv50_ir::ValueDef>&, unsigned long) /usr/include/c++/9/bits/alloc_traits.h:444 #3 0x7f1d1214dbd3 in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_allocate_node() /usr/include/c++/9/bits/stl_deque.h:617 #4 0x7f1d1214c464 in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_create_nodes(nv50_ir::ValueDef**, nv50_ir::ValueDef**) (/home/kherbst/local/lib64/dri//nouveau_dri.so+0x829464) #5 0x7f1d121495cd in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_M_initialize_map(unsigned long) /usr/include/c++/9/bits/stl_deque.h:716 #6 0x7f1d12146f7d in std::_Deque_base<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::_Deque_base() /usr/include/c++/9/bits/stl_deque.h:507 #7 0x7f1d1214518d in std::deque<nv50_ir::ValueDef, std::allocator<nv50_ir::ValueDef> >::deque() /usr/include/c++/9/bits/stl_deque.h:912 #8 0x7f1d1213b9c9 in nv50_ir::Instruction::Instruction(nv50_ir::Function*, nv50_ir::operation, nv50_ir::DataType) ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:605 #9 0x7f1d1224dd44 in nv50_ir::Function::convertToSSA() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ssa.cpp:385 #10 0x7f1d1224d381 in nv50_ir::Program::convertToSSA() ../src/gallium/drivers/nouveau/codegen/nv50_ir_ssa.cpp:310 #11 0x7f1d121407c0 in nv50_ir_generate_code ../src/gallium/drivers/nouveau/codegen/nv50_ir.cpp:1264 #12 0x7f1d1227461b in nvc0_program_translate ../src/gallium/drivers/nouveau/nvc0/nvc0_program.c:634 #13 0x7f1d12294b21 in nvc0_sp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:620 #14 0x7f1d12294d90 in nvc0_fp_state_create ../src/gallium/drivers/nouveau/nvc0/nvc0_state.c:661 #15 0x7f1d12ad4912 in st_create_fp_variant ../src/mesa/state_tracker/st_program.c:1498 #16 0x7f1d12ad4cd5 in st_get_fp_variant ../src/mesa/state_tracker/st_program.c:1525 #17 0x7f1d12ad8252 in st_precompile_shader_variant ../src/mesa/state_tracker/st_program.c:2053 #18 0x7f1d12c9c851 in st_program_string_notify ../src/mesa/state_tracker/st_cb_program.c:185 #19 0x7f1d12d17731 in st_link_tgsi ../src/mesa/state_tracker/st_glsl_to_tgsi.cpp:7441 #20 0x7f1d12cabaf0 in st_link_shader ../src/mesa/state_tracker/st_glsl_to_ir.cpp:175 #21 0x7f1d127c85ca in _mesa_glsl_link_shader ../src/mesa/program/ir_to_mesa.cpp:3186 #22 0x7f1d1252a9f7 in link_program ../src/mesa/main/shaderapi.c:1285 #23 0x7f1d1252a9f7 in link_program_error ../src/mesa/main/shaderapi.c:1384 #24 0x7f1d1252deb3 in _mesa_LinkProgram ../src/mesa/main/shaderapi.c:1876 #25 0x403e13 in main._omp_fn.0 /home/kherbst/git/shader-db/run.c:926 SUMMARY: AddressSanitizer: heap-use-after-free ../src/gallium/drivers/nouveau/codegen/nv50_ir.h:648 in nv50_ir::ValueDef::get() const Shadow bytes around the buggy address: 0x0c2a80075420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x0c2a80075430: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x0c2a80075440: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0x0c2a80075450: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fa 0x0c2a80075460: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa =>0x0c2a80075470:[fd]fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd 0x0c2a80075480: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd 0x0c2a80075490: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd 0x0c2a800754a0: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fa 0x0c2a800754b0: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa 0x0c2a800754c0: fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd Shadow byte legend (one shadow byte represents 8 application bytes): Addressable: 00 Partially addressable: 01 02 03 04 05 06 07 Heap left redzone: fa Freed heap region: fd Stack left redzone: f1 Stack mid redzone: f2 Stack right redzone: f3 Stack after return: f5 Stack use after scope: f8 Global redzone: f9 Global init order: f6 Poisoned by user: f7 Container overflow: fc Array cookie: ac Intra object redzone: bb ASan internal: fe Left alloca redzone: ca Right alloca redzone: cb Shadow gap: cc ==612087==ABORTING v2: full rework v3: manage a full copy instead of recreating new lists on every access Closes: #3066 Signed-off-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5277>
* nv50/ir/ra: convert some for loops to Range-based for loopsKarol Herbst2020-06-221-11/+8
| | | | | | | I will touch them in the next commit Signed-off-by: Karol Herbst <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5277>
* panfrost: Copy resources when mapping to avoid waiting for readersIcecream952020-06-221-1/+23
| | | | | | | | | | | It is often faster to copy the whole resource and modify that than to flush and wait for readers of the BO. Helps anything which updates textures after already using them in a frame, such as most GLQuake ports. Reviewed-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>
* panfrost: Update sampler views when the texture bo changesIcecream952020-06-223-1/+4
| | | | | | | | | | | The BO reallocation path in panfrost_transfer_map caused textures and sampler views to get out of sync. v2: Use the GPU address of the BO in case two BOs get allocated at the same address. Reviewed-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>
* panfrost: RGBA4 and RGB5_A1 framebuffer supportIcecream952020-06-223-0/+6
| | | | | | | Tested with fbo_firecube. Reviewed-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>
* pan/mdg: Fix max_comp calculation for constant printingIcecream952020-06-221-1/+1
| | | | | Reviewed-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>
* pan/decode: Add missing wrap modesIcecream952020-06-221-0/+4
| | | | | Reviewed-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>
* pan/decode: Fix helper invocations when tracingIcecream952020-06-221-2/+2
| | | | | | | | | | | midgard1.flags_lo was being changed when tracing, causing helper invocations to be disabled. This was found by using mprotect to make BOs read only in pandecode_fetch_gpu_mem. Reviewed-by: Tomeu Vizoso <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5573>
* r600/sfn: Don't set num_components on TESS sysvalue intrinsicsGert Wollny2020-06-222-12/+8
| | | | | | | | | | | | These instructions are not vectorized, and validation rules added for this with 167fa2887f09 nir/validate: validate intr->num_components Fixes: 46a3033b43b9b51cae5c60eea39e7e5af325c4db r600/sfn: Emit some LDS instructions Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>
* r600/sfn: Add support for shared atomicsGert Wollny2020-06-226-0/+164
| | | | | Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>
* r600/sfn: Add lowering pass for shared IOGert Wollny2020-06-221-0/+90
| | | | | | | Lower shared load and store to use the r600 specific intrinsics. Signed-off-by: Gert Wollny <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-05 00:17:16 +0000