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* i965,iris/blorp: do not blit 0-sizesSergii Romantsov2019-03-302-2/+18
| | | | | | | | | | | | | | | | | Seems there is no sense in blitting 0-sized sources or destinations. Additionaly it may cause segfaults for i965. v2: Function call replaced with inline check v3: Added check to avoid devision by zero (L. Landwerlin) v4: Added simillar check for Iris (L. Landwerlin) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110239 Signed-off-by: Sergii Romantsov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* gallium: Fix autotools build with libxatracker.la.Vinson Lee2019-03-291-4/+2
| | | | | | | | | | | CXXLD libxatracker.la /usr/bin/ld: ../../../../src/gallium/auxiliary/.libs/libgallium.a(tgsi_to_nir.o): in function `ttn_finalize_nir': src/gallium/auxiliary/nir/tgsi_to_nir.c:2111: undefined reference to `gl_nir_lower_samplers_as_deref' /usr/bin/ld: src/gallium/auxiliary/nir/tgsi_to_nir.c:2113: undefined reference to `gl_nir_lower_samplers' Fixes: 9a834447d652 ("tgsi_to_nir: Produce optimized NIR for a given pipe_screen.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109929 Signed-off-by: Vinson Lee <[email protected]>
* gallium: fix autotools build of pipe_msm.laTimur Kristóf2019-03-291-4/+2
| | | | | | Signed-off-by: Vinson Lee <[email protected]> Fixes: 9a834447d652 ("tgsi_to_nir: Produce optimized NIR for a given pipe_screen.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109929
* nir: Lock around validation fail shader dumpingJason Ekstrand2019-03-291-0/+10
| | | | | | | This prevents getting mixed-up results if a multi-threaded app has two validation errors in different threads. Reviewed-by: Timothy Arceri <[email protected]>
* util: no-op __builtin_types_compatible_p() for non-GCC compilersBrian Paul2019-03-291-0/+4
| | | | | | | | | | | | | | __builtin_types_compatible_p() is GCC-specific and breaks the MSVC build. This intrinsic has been in u_vector_foreach() for a long time, but that macro has only recently been used in code (nir/nir_opt_comparison_pre.c) that's built with MSVC. Fixes: 2cf59861a ("nir: Add partial redundancy elimination for compares") Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* iris: Clean up compiler warnings about unusedCaio Marcelo de Oliveira Filho2019-03-292-11/+1
| | | | | | | Removed a few unused variables and iris_getparam_boolean(). Kept 'name' around since there's a commented debug that make use of it. Reviewed-by: Kenneth Graunke <[email protected]>
* egl: hide entrypoints that shouldn't be exported when using glvndEric Engestrom2019-03-291-0/+6
| | | | | | | | | | | From GLVND author: > From a functional standpoint, exporting additional symbols doesn't > really matter, since libglvnd will load the vendor libraries with > RTLD_LOCAL. Suggested-by: Kyle Brenneman <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Kyle Brenneman <[email protected]>
* nir/validate: validate that tex deref sources are actually derefsKarol Herbst2019-03-291-0/+11
| | | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir/print: fix printing the image_array intrinsic indexKarol Herbst2019-03-291-2/+2
| | | | | | | Fixes: 0de003be0363 ("nir: Add handle/index-based image intrinsics") Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "ac/nir: use new LLVM 8 intrinsics for SSBO atomic operations"Timothy Arceri2019-03-291-42/+24
| | | | | | | | | This reverts commit 29132af2347ede46a6d02422295a5fadbe5fe788. It seems the new intrinsic causes a hang on radeonsi (VEGA) when running the piglit test: tests/spec/arb_shader_storage_buffer_object/execution/ssbo-atomicCompSwap-int.shader_test
* ac: fix return type for llvm.amdgcn.frexp.exp.i32.64Samuel Pitoiset2019-03-291-1/+1
| | | | | | | | This fixes the following piglit with RadeonSI tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-frexp-dvec4.shader_test Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* virgl: Add a caps feature check versionGert Wollny2019-03-293-1/+4
| | | | | | | | | | | | | | | | | | When we add new feature checks on the host side that is used to enable a cap conditionally that was enabled unconditionally before we might end up with a feature regression when a new mesa version is used with an old virglrenderer version that doesn't check for that cap. To work around this problem add a version id to the caps that corresponds to the features that are actually checked on the host and check that version too when enabling the cap. Fixes: 2ee197d6e84aa37638d423363aca183952816067 virgl: Enable mixed color FBO attachemnets only when the host supports it Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Pohsien Wang <[email protected]>
* radv: do not always initialize HTILE in compressed stateSamuel Pitoiset2019-03-291-2/+8
| | | | | | | | | | | | Especially when performing a transtion from UNDEFINED->GENERAL, the driver shouldn't initialize HTILE metadata in compressed state because it doesn't decompress when the src layout is GENERAL. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110259 Fixes: 3a2e93147f7 ("radv: always initialize HTILE when the src layout is UNDEFINED") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* iris: Print the memzone name when allocating BOs with INTEL_DEBUG=bufKenneth Graunke2019-03-281-2/+17
| | | | | This gives me an idea of what kinds of buffers are being allocated on the fly which could help inform our cache decisions.
* nir: use {0} initializer instead of {} to fix MSVC buildBrian Paul2019-03-281-2/+2
| | | | | | Trivial change. Fixes: c6ee46a75 ("nir: Add nir_alu_srcs_negative_equal")
* intel/compiler: Use partial redundancy elimination for comparesIan Romanick2019-03-281-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all of the hurt shaders are repeated instances of the same shader in synmark's compilation speed tests. shader-db results: All Gen6+ platforms had similar results. (Skylake shown) total instructions in shared programs: 15256840 -> 15256389 (<.01%) instructions in affected programs: 54137 -> 53686 (-0.83%) helped: 288 HURT: 0 helped stats (abs) min: 1 max: 15 x̄: 1.57 x̃: 1 helped stats (rel) min: 0.06% max: 26.67% x̄: 1.99% x̃: 0.74% 95% mean confidence interval for instructions value: -1.76 -1.38 95% mean confidence interval for instructions %-change: -2.47% -1.50% Instructions are helped. total cycles in shared programs: 372286583 -> 372283851 (<.01%) cycles in affected programs: 833829 -> 831097 (-0.33%) helped: 265 HURT: 16 helped stats (abs) min: 2 max: 74 x̄: 11.81 x̃: 4 helped stats (rel) min: 0.04% max: 9.07% x̄: 0.99% x̃: 0.35% HURT stats (abs) min: 2 max: 130 x̄: 24.88 x̃: 8 HURT stats (rel) min: <.01% max: 12.31% x̄: 1.44% x̃: 0.27% 95% mean confidence interval for cycles value: -12.30 -7.15 95% mean confidence interval for cycles %-change: -1.06% -0.64% Cycles are helped. Iron Lake and GM45 had similar results. (GM45 shown) total instructions in shared programs: 5038653 -> 5038495 (<.01%) instructions in affected programs: 13939 -> 13781 (-1.13%) helped: 50 HURT: 1 helped stats (abs) min: 1 max: 15 x̄: 3.18 x̃: 4 helped stats (rel) min: 0.33% max: 13.33% x̄: 2.24% x̃: 1.09% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 0.83% max: 0.83% x̄: 0.83% x̃: 0.83% 95% mean confidence interval for instructions value: -3.73 -2.47 95% mean confidence interval for instructions %-change: -3.16% -1.21% Instructions are helped. total cycles in shared programs: 128118922 -> 128118228 (<.01%) cycles in affected programs: 134906 -> 134212 (-0.51%) helped: 50 HURT: 0 helped stats (abs) min: 2 max: 60 x̄: 13.88 x̃: 18 helped stats (rel) min: 0.06% max: 3.19% x̄: 0.74% x̃: 0.70% 95% mean confidence interval for cycles value: -16.54 -11.22 95% mean confidence interval for cycles %-change: -0.95% -0.53% Cycles are helped. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add partial redundancy elimination for comparesIan Romanick2019-03-285-0/+414
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass attempts to dectect code sequences like if (x < y) { z = y - x; ... } and replace them with sequences like t = x - y; if (t < 0) { z = -t; ... } On architectures where the subtract can generate the flags used by the if-statement, this saves an instruction. It's also possible that moving an instruction out of the if-statement will allow nir_opt_peephole_select to convert the whole thing to a bcsel. Currently only floating point compares and adds are supported. Adding support for integer will be a challenge due to integer overflow. There are a couple possible solutions, but they may not apply to all architectures. v2: Fix a typo in the commit message and a couple typos in comments. Fix possible NULL pointer deref from result of push_block(). Add missing (-A + B) case. Suggested by Caio. v3: Fix is_not_const_zero to work correctly with types other than nir_type_float32. Suggested by Ken. v4: Add some comments explaining how this works. Suggested by Ken. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add nir_alu_srcs_negative_equalIan Romanick2019-03-283-0/+192
| | | | | | | v2: Move bug fix in get_neg_instr from the next patch to this patch (where it was intended to be in the first place). Noticed by Caio. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add nir_const_value_negative_equalIan Romanick2019-03-284-0/+398
| | | | | | | v2: Rebase on 1-bit Boolean changes. Reviewed-by: Thomas Helland <[email protected]> [v1] Reviewed-by: Kenneth Graunke <[email protected]>
* nir/algebraic: Add missing 16-bit extract_[iu]8 patternsIan Romanick2019-03-281-0/+3
| | | | | | | | | | | | | | No shader-db changes on any Intel platform. v2: Use a loop to generate patterns. Suggested by Jason. v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would replace an extract_i8 with and extract_u8. This broke ~180 tests. This bug was introduced in v2. Reviewed-by: Matt Turner <[email protected]> [v1] Reviewed-by: Dylan Baker <[email protected]> [v2] Acked-by: Jason Ekstrand <[email protected]> [v2]
* nir/algebraic: Add missing 64-bit extract_[iu]8 patternsIan Romanick2019-03-281-0/+3
| | | | | | | | | | | | | | No shader-db changes on any Intel platform. v2: Use a loop to generate patterns. Suggested by Jason. v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would replace an extract_i8 with and extract_u8. This broke ~180 tests. This bug was introduced in v2. Reviewed-by: Matt Turner <[email protected]> [v1] Reviewed-by: Dylan Baker <[email protected]> [v2] Acked-by: Jason Ekstrand <[email protected]> [v2]
* nir/algebraic: Remove redundant extract_[iu]8 patternsIan Romanick2019-03-281-14/+4
| | | | | | | | No shader-db changes on any Intel platform. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* nir/algebraic: Fix up extract_[iu]8 after loop unrollingIan Romanick2019-03-281-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Skylake, Broadwell, and Haswell had similar results. (Skylake shown) total instructions in shared programs: 15256840 -> 15256837 (<.01%) instructions in affected programs: 4713 -> 4710 (-0.06%) helped: 3 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.06% max: 0.08% x̄: 0.06% x̃: 0.06% total cycles in shared programs: 372286583 -> 372286583 (0.00%) cycles in affected programs: 198516 -> 198516 (0.00%) helped: 1 HURT: 1 helped stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10 helped stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01% HURT stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10 HURT stats (rel) min: 0.01% max: 0.01% x̄: 0.01% x̃: 0.01% No changes on any other Intel platform. v2: Use a loop to generate patterns. Suggested by Jason. v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would replace an extract_i8 with and extract_u8. This broke ~180 tests. This bug was introduced in v2. Reviewed-by: Matt Turner <[email protected]> [v1] Reviewed-by: Dylan Baker <[email protected]> [v2] Acked-by: Jason Ekstrand <[email protected]> [v2]
* nir/deref: fix struct wrapper casts. (v3)Dave Airlie2019-03-291-2/+36
| | | | | | | | | | | llvm/spir-v spits out some struct a { struct b {} }, but it doesn't deref, it casts (struct a) to (struct b), reconstruct struct derefs instead of casts for these. v2: use ssa_def_rewrite uses, rework the type restrictions (Jason) v3: squish more stuff into one function, drop unused temp (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Remove unused parameter from blorp_surf_for_miptree.Rafael Antognolli2019-03-281-24/+12
| | | | | | It seems pretty useless nowadays. Reviewed-by: Jason Ekstrand <[email protected]>
* iris/icl: Add WA_2204188704 to disable pixel shader panic dispatchAnuj Phogat2019-03-281-0/+7
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris/icl: Set Enabled Texel Offset Precision Fix bitAnuj Phogat2019-03-281-0/+7
| | | | | | | | h/w specification requires this bit to be always set. See Mesa commit 5eb173304bd. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* freedreno/ir3: align const size to vec4Rob Clark2019-03-281-4/+5
| | | | | | | This is no longer true since PIPE_CAP_PACKED_UNIFORMS was enabled. Fixes: 3c8779af325 freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: reads/writes to unrelated arrays are not dependentRob Clark2019-03-281-1/+30
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: sched fixRob Clark2019-03-281-1/+1
| | | | | | | Not sure why new-style frag inputs start triggering this. But we probably shouldn't consider src's from other blocks. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: small cleanupRob Clark2019-03-281-2/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* iris: Fix blits with S8_UINT destinationKenneth Graunke2019-03-281-4/+2
| | | | | | | | | | | | For depth and stencil blits, we always want the main mask to be Z, and the secondary pass mask to be S. If asked to blit Z+S to S, we should handle the blit in the second pass which properly gets the stencil resources. Before, we were trying to handle S as the main mask, and accidentally blitting a Z source to a S destination, which doesn't work out well. Fixes Piglit's "framebuffer-blit-levels {draw,read} stencil" tests.
* st/mesa: Fix blitting from GL_DEPTH_STENCIL to GL_STENCIL_INDEXKenneth Graunke2019-03-281-0/+1
| | | | | | | | | Fixes assertion failures in Piglit's "framebuffer-blit-levels {draw,read} stencil" tests on iris. Also fixes assert failures in frameretrace, which tries to ReadPixels the stencil values (only) from a Z24S8 depth/stencil attachment. Reviewed-by: Kristian H. Kristensen <[email protected]>
* freedreno/ir3: Add workaround for VS samgqKristian H. Kristensen2019-03-286-4/+29
| | | | | | | | | | | | | | | | | This instruction needs a workaround when used from vertex shaders. Fixes: dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler2dshadow_vertex dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_fixed_vertex dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_float_vertex dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler2dshadow_vertex dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_fixed_vertex dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_float_vertex dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.sampler2dshadow_vertex Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/ir3: Don't access beyond available regsKristian H. Kristensen2019-03-281-4/+7
| | | | | | | | emit_cat5() needs to check if the last optional reg is there before it accesses it. Signed-off-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* util/disk_cache: close fd in the fallback pathEric Engestrom2019-03-281-4/+3
| | | | | | | | | There are multiple `goto path_fail` with an open fd, but none that go to `fail:` without going through `path_fail:` first, so let's just move the `close(fd)` there. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radv: skip updating depth/color metadata for conditional renderingSamuel Pitoiset2019-03-281-3/+3
| | | | | | | | | | | | I don't think we should update metadata when conditional rendering is enabled. For some reasons, some CTS breaks only on SI. This fixes the following CTS on SI: dEQP-VK.conditional_rendering.draw_clear.clear.depth.* Cc: 19.0 <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* st/nir: Free the GLSL IR after linking.Kenneth Graunke2019-03-281-0/+4
| | | | | | | | | i965 does this, and st's tgsi path does this. st/nir did not. Cuts 138MB of memory from a DiRT Rally trace, which is about 44% of the total GLSL IR memory. Reviewed-by: Timothy Arceri <[email protected]>
* radv: enable VK_AMD_gpu_shader_int16Samuel Pitoiset2019-03-281-0/+1
| | | | | | | This extension allows 16-bit support to Frexp/FrexpStruct. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not lower frexp_exp and frexp_sigSamuel Pitoiset2019-03-281-1/+0
| | | | | | | Hardware has two instructions. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add ac_build_frex_exp() helper ans 16-bit/32-bit supportSamuel Pitoiset2019-03-283-3/+33
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add ac_build_frexp_mant() helper and 16-bit/32-bit supportSamuel Pitoiset2019-03-283-2/+31
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* iris: Actually advertise some modifiersKenneth Graunke2019-03-271-0/+39
| | | | | | | | | | I neglected to fill out this driver function, causing us to advertise 0 modifiers. Now we advertise the various tilings and let the driver pick them. I've verified that X tiling works with Weston (by hacking the list to skip Y tiling). Y+CCS doesn't work yet because it's multiplane and the Gallium dri state tracker isn't really prepared for that. Leave it off for now.
* intel/genxml: Media instructions and structures for gen11Toni Lönnberg2019-03-281-24/+3450
| | | | | | | | | | | v2: Lionel Landwerlin <[email protected]> - fix missing type - fix *_FQM_*/*_QM_* commands - shorten some media structs using groups - factor out memory attributes - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Media instructions and structures for gen10Toni Lönnberg2019-03-281-24/+3284
| | | | | | | | | | | v2: Lionel Landwerlin <[email protected]> - fix missing type - fix *_FQM_*/*_QM_* commands - shorten some media structs using groups - factor out memory attributes - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Media instructions and structures for gen9Toni Lönnberg2019-03-281-24/+3090
| | | | | | | | | | | v2: Lionel Landwerlin <[email protected]> - fix missing type - fix *_FQM_*/*_QM_* commands - shorten some media structs using groups - factor out memory attributes - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Media instructions and structures for gen8Toni Lönnberg2019-03-281-0/+1572
| | | | | | | v2: Lionel Landwerlin <[email protected]> - switch MI_FLUSH_DW fields to bool Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Media instructions and structures for gen7.5Toni Lönnberg2019-03-281-1/+1291
| | | | | | v2: Fixed MI_WAIT_FOR_EVENT to be for video also Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Media instructions and structures for gen7Toni Lönnberg2019-03-281-1/+1347
| | | | | | v2: Fixed MI_WAIT_FOR_EVENT to be for blitter and video also Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/genxml: Media instructions and structures for gen6Toni Lönnberg2019-03-281-1/+1003
| | | | | | v2: Fixed MI_WAIT_FOR_EVENT to be for blitter and video also Reviewed-by: Lionel Landwerlin <[email protected]>
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