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* llvmpipe: decrease MAX_SCENES from 2 to 1Roland Scheidegger2014-12-062-1/+13
| | | | | | | | | | | | | | | | | | Multiple scenes per context are meant to be used so a new scene can be built while another one is processed in rasterization. However, quite surprisingly, this does not actually work (and according to git log, possibly never did, though maybe it did at some point further back (5 years+) but was buggy) because we always wait immediately on the rasterizer to finish the scene when contexts (and hence setup/scene) is flushed. This means when we try to get an empty scene later, any old one is already empty again. Thus using multiple scenes is just a waste of memory (not too bad, since the additional scenes are guaranteed to be empty, which means their size ought to be one data block (64kB) plus the size of some structs), without actually really doing anything. (There is also quite some code for the whole concept of multiple scenes which doesn't really do much in practice, but keep it hoping the wait-on-scene-flush can be fixed some day.) Reviewed-by: Jose Fonseca <[email protected]>
* draw: use the prim type from prim_info not emit in passthrough emitRoland Scheidegger2014-12-061-2/+2
| | | | | | | | | | | | The prim assembler may change the prim type when injecting prim ids now, which isn't reflected by what's stored in emit. This looks brittle and potentially dangerous (it is not obvious if such prim type changes are really supported by pt emit, the prim type is actually also set in prepare which would then be different). This fixes piglit primitive-id-no-gs-first-vertex.shader_test. Reviewed-by: Jose Fonseca <[email protected]>
* draw: use correct output prim for non-adjacent topologies in prim assembler.Roland Scheidegger2014-12-061-4/+4
| | | | | | | | | | | | | | | | | The decomposition done in the prim assembler will turn tri fans into tris, but this wasn't reflected in the output prim type. Meaning with a tri fan with 6 verts input, the output was a tri fan with 12 vertices instead of a tri list with 12 vertices (not as bad as it sounds, since the additional tris created would all be degenerate since they'd all have two times vertex zero but still bogus). This is because the prim assembler is used if either the input topology is something with adjacency, or if prim id needs to be injected, and for the latter case topologies without adjacency can be converted to basic ones. Unfortunately decomposition here for inserting prim ids is necessary, at least for the indexed case where we can't just insert the prim id at the right place depending on provoking vertex. Reviewed-by: Jose Fonseca <[email protected]>
* draw: kill off unneded prim assembler code for handling adjacency vertsRoland Scheidegger2014-12-062-60/+0
| | | | | | | | The default macros when the adjacency macros aren't defined will already exactly do that (that is, drop the adjacent vertices and call the non-adjacent macro). Reviewed-by: Jose Fonseca <[email protected]>
* gallium/docs: (trivial) remove STR opcode description.Roland Scheidegger2014-12-061-9/+0
| | | | | The opcode was removed alongside SFL by commit ecfe9e2ad2b5f178ef09420f8d95d49937137cd9.
* i965/fs: Perform CSE on MOV ..., VF instructions.Matt Turner2014-12-051-5/+11
| | | | | | | | | | | Safe from causing optimization loops, since we don't constant propagate VF arguments. (for this and the previous patch): total instructions in shared programs: 4289075 -> 4271932 (-0.40%) instructions in affected programs: 1616779 -> 1599636 (-1.06%) Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Try to emit LINE instructions on Gen <= 5.Matt Turner2014-12-052-0/+56
| | | | | | | | | | | | | The LINE instruction performs a multiply-add instruction (a * b + c) where b and c are scalar arguments. It reads b and c from offsets in src0 such that you can load them (it they're representable) as a vector-float immediate with a single instruction. Hurts some programs, but that'll all get better once we CSE the vector-float MOVs in the next patch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77544 Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add support for generating the LINE instruction.Matt Turner2014-12-051-0/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* i965: Set the region of LINE's src0 to <0,1,0>.Matt Turner2014-12-051-1/+10
| | | | | | | | | | | | | The PRMs say that <src0> region must be a replicated scalar (with HorzStride = VertStride = 0). but apparently that doesn't actually apply to all generations. I did notice when implementing the optimization later in this series that G45 and ILK needed this regioning. Reviewed-by: Ian Romanick <[email protected]>
* i965: Give compile stats through KHR_debug.Matt Turner2014-12-052-0/+20
| | | | Reviewed-by: Ian Romanick <[email protected]>
* mesa: Add a source parameter to _mesa_gl_debug.Matt Turner2014-12-057-2/+12
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* vc4: Try swapping the regfile A to B to pair instructions.Eric Anholt2014-12-051-2/+62
| | | | | total instructions in shared programs: 56995 -> 56087 (-1.59%) instructions in affected programs: 40503 -> 39595 (-2.24%)
* vc4: Allow pairing of some instructions that disagree about the WS bit.Eric Anholt2014-12-051-1/+47
| | | | | No difference on shader-db because we tend to have a lot of other conflicts going on as well (like RADDR_A disagreements)
* configure.ac: Replace contraction to fix syntax highlighting.Matt Turner2014-12-051-1/+1
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* i965/gs: Avoid DW * DW mulBen Widawsky2014-12-051-2/+6
| | | | | | | | | | | | | | | | | | | | | | | The GS has an interesting use for mul. Because the GS can emit multiple vertices per input vertex, and it also has a unique count at the top of the URB payload, the GS unit needs to be able to dynamically specify URB write offsets (relative to the global offset). The documentation in the function has a very good explanation from Paul on the mechanics. This fixes around 2000 piglit tests on BSW. v2: Reworded commit message (Ben) no mention of CHV (Matt) Change SHRT_MAX to USHRT_MAX (Ken, and Matt) Update comment in code to reflect the use of UW (Ben) Add Gen7+ assertion for the relevant GS code, since it won't work on Gen6- (Ken) Drop the bogus hunk in emit_control_data_bits() (Ken) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84777 (with many dupes) Cc: "10.4 10.3 10.2" <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* vc4: Add separate write-after-read dependency tracking for pairing.Eric Anholt2014-12-051-20/+58
| | | | | | | | | If an operation is the last one to read a register, the instruction containing it can also include the op that has the next write to that register. total instructions in shared programs: 57486 -> 56995 (-0.85%) instructions in affected programs: 43004 -> 42513 (-1.14%)
* vc4: Fix inverted priority of instructions for QPU scheduling.Eric Anholt2014-12-051-10/+10
| | | | | | | | | | | We were scheduling TLB operations as early as possible, and texture setup as late as possible. When I introduced prioritization, I visually inspected that an independent operation got moved above texture results collection, which tricked me into thinking it was working (but it was just because texture setup was being pushed late). total instructions in shared programs: 57651 -> 57486 (-0.29%) instructions in affected programs: 18532 -> 18367 (-0.89%)
* vc4: Refuse to merge two ops that both access shared functions.Eric Anholt2014-12-053-36/+55
| | | | | Avoids assertion failures in vc4_qpu_validate.c if we happen to find the right set of operations available.
* vc4: Allow dead code elimination of color reads.Eric Anholt2014-12-051-1/+1
| | | | | This might happen if the blending functions are set up to not actually use the destination color/alpha, for example.
* vc4: Add a debug flag for waiting for sync on submit.Eric Anholt2014-12-053-0/+11
| | | | | This is nice when you're tracking down which command list is hanging the GPU.
* i965/fs: Move brw_file_from_reg() higher in the file.Matt Turner2014-12-051-14/+14
| | | | This was supposed to be part of the previous commit.
* i965/fs: Make brw_reg_from_fs_reg static and remove prototype.Matt Turner2014-12-052-72/+70
| | | | | | And move it above its first use in brw_fs_generator.cpp. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use ~0 to represent true on all generations.Matt Turner2014-12-055-102/+120
| | | | | | | | | | | | | | Jason realized that we could fix the result of the CMP instruction on Gen <= 5 by doing -(result & 1). Also do the resolves in the vec4 backend before use, rather than when the bool was created. The FS does this and it saves some unnecessary resolves. On Ironlake: total instructions in shared programs: 4289762 -> 4287277 (-0.06%) instructions in affected programs: 619430 -> 616945 (-0.40%) Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Change the type of booleans to D.Matt Turner2014-12-053-25/+25
| | | | | | | | | | This is a revert of commit 4656c14e ("i965/fs: Change the type of booleans to UD and emit correct immediates") plus some small additional fixes, like casting ctx->Const.UniformBooleanTrue to int and changing UD to D in the ir_unop_b2f cases. Note that it's safe to leave 0x3f800000 as UD and as a literal it's more recognizable than 1065353216. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Add a negate() function.Matt Turner2014-12-051-0/+8
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Don't DCE flag-writing insts because dest was unused.Matt Turner2014-12-051-1/+1
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Allow CSE on uniform-vec4 expansion MOVs.Matt Turner2014-12-056-1/+13
| | | | | | | | | | | | | | | | | | | | | | Three source instructions cannot directly source a packed vec4 (<0,4,1> regioning) like vec4 uniforms, so we emit a MOV that expands the vec4 to both halves of a register. If these uniform values are used by multiple three-source instructions, we'll emit multiple expansion moves, which we cannot combine in CSE (because CSE emits moves itself). So emit a virtual instruction that we can CSE. Sometimes we demote a uniform to to a pull constant after emitting an expansion move for it. In that case, recognize in opt_algebraic that if the .file of the new instruction is GRF then it's just a real move that we can copy propagate and such. total instructions in shared programs: 5822418 -> 5812335 (-0.17%) instructions in affected programs: 351841 -> 341758 (-2.87%) Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Optimize scalar all_equal/any_nequal into equal/nequal.Matt Turner2014-12-051-0/+10
| | | | | | | | | Cuts an instruction from two shaders in Tesseract, by allowing the (x+y) cmp 0 -> x cmp -y optimization to take place. instructions in affected programs: 1198 -> 1194 (-0.33%) Reviewed-by: Eric Anholt <[email protected]>
* mesa: Ensure stack is realigned on x86.José Fonseca2014-12-051-0/+3
| | | | | | | | | | | | | | | | | | | | Nowadays GCC assumes stack pointer is 16-byte aligned even on 32-bits, but that is an assumption OpenGL drivers (or any dynamic library for that matter) can't afford to make as there are many closed- and open- source application binaries out there that only assume 4-byte stack alignment. This fix uses force_align_arg_pointer GCC attribute, and is only a stop-gap measure. The right fix would be to pass -mstackrealign or -mincoming-stack-boundary=2 to all source fails that use any -msse* option, as there is no way to guarantee if/when GCC will decide to spill SSE registers to the stack. https://bugs.freedesktop.org/show_bug.cgi?id=86788 Reviewed-by: Brian Paul <[email protected]>
* util/primconvert: Avoid point arithmetic; apply offset on all cases.José Fonseca2014-12-051-1/+2
| | | | | | Matches what u_vbuf_get_minmax_index() does. Reviewed-by: Ilia Mirkin <[email protected]>
* util/primconvert: take ib offset into accountIlia Mirkin2014-12-051-1/+1
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.3" <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* util/primconvert: support instanced renderingIlia Mirkin2014-12-051-0/+2
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.3 10.4" <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* util/primconvert: pass index bias throughIlia Mirkin2014-12-051-0/+1
| | | | | | | | | | The index_bias (aka base_vertex) applies to the downstream draw just as much, since the actual index values are never modified. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.3 10.4" <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* i965: Compute VS attribute WA bits earlier and check if they changed.Kenneth Graunke2014-12-044-37/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BRW_NEW_VERTICES is flagged every time we draw a primitive. Having the brw_vs_prog atom depend on BRW_NEW_VERTICES meant that we had to compute the VS program key and do a program cache lookup for every single primitive. This is painfully expensive. The workaround bit computation is almost entirely based on the vertex attribute arrays (brw->vb.inputs[i]), which are set by brw_merge_inputs. The only thing it uses the VS program for is to see which VS inputs are actually read. brw_merge_inputs() happens once per primitive, and can safely look at the currently bound vertex program, as it doesn't change in the middle of a draw. This patch moves the workaround bit computation to brw_merge_inputs(), right after assigning brw->vb.inputs[i], and stores the previous WA bit values in the context. If they've actually changed from the last draw (which is uncommon), we signal that we need a new vertex program, causing brw_vs_prog to compute a new key. Improves performance in Gl32Batch7 by 13.6123% +/- 0.739652% (n=166) on Haswell GT3e. I'm told Baytrail shows similar gains. v2: Introduce a new BRW_NEW_VS_ATTRIB_WORKAROUNDS dirty bit, rather than reusing BRW_NEW_VERTEX_PROGRAM (suggested by Chris Forbes). This prevents unnecessary re-emission of surface/sampler related atoms (and an SOL atom on Sandybridge). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* egl/dri2: Log a warning if no platforms are enabled.Matt Turner2014-12-041-0/+1
| | | | | | | | | If you hit this, you didn't compile with --with-egl-platforms=... Recompile with something like --with-egl-platforms=x11,drm and make clean and make again. Reviewed-by: Anuj Phogat <[email protected]>
* i965: Drop BRW_NEW_VERTEX_PROGRAM and _NEW_TRANSFORM from Gen4 VS state.Kenneth Graunke2014-12-041-3/+2
| | | | | | | | | | These stopped being necessary in commit ab973403e445cd8211dba4e87e0. v2: Update commit message with a better explanation (thanks to Eric Anholt for doing the git archaeology). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Drop BRW_NEW_VERTEX_PROGRAM from Gen7+ 3DSTATE_VS atoms.Kenneth Graunke2014-12-042-2/+0
| | | | | | | | | | | We don't access brw->vertex_program or ctx->_Shader since the previous commit, so we don't need this dirty bit. I think it's still necessary on Gen6 because it still conflates constant uploading with unit state uploading. We can fix that later. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Store floating point mode choice in brw_stage_prog_data.Kenneth Graunke2014-12-0411-43/+18
| | | | | | | | | | | | | | | | | | | | | | | | We use IEEE mode for GLSL programs, but need to use ALT mode for ARB programs so that 0^0 == 1. The choice is based entirely on the shader source language. Previously, our code to determine which mode we wanted was duplicated in 8 different places (VS and FS for Gen4-5, Gen6, Gen7, and Gen8). The ctx->_Shader->CurrentProgram[stage] == NULL check was confusing as well - we use CurrentProgram (non-derived state), but _Shader (derived state). It also relies on knowing that ARB programs don't use gl_shader_program structures today. The compiler already makes this assumption in a few places, but I'd rather keep that assumption out of the state upload code. With this patch, we select the mode at compile time, and store that choice in prog_data. The state upload code simply uses that decision. This eliminates a BRW_NEW_*_PROGRAM dependency in the state upload code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Make Gen4-5 and Gen8+ ALT checks use ctx->_Shader too.Kenneth Graunke2014-12-044-4/+4
| | | | | | | | | | | | | Commit c0347705 changed the Gen6-7 code to use ctx->_Shader rather than ctx->Shader, but neglected to change the Gen4-5 or Gen8+ code. This might fix SSO related bugs, but ALT mode is only used for ARB programs, so if there's an actual problem, it's likely no one would run into it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Move PSCDEPTH calculations from draw time to compile time.Kenneth Graunke2014-12-046-52/+40
| | | | | | | | | | | | | | | The "Pixel Shader Computed Depth Mode" value is entirely based on the shader program, so we can easily do it at compile time. This avoids the if+switch on every 3DSTATE_WM (Gen7)/3DSTATE_PS_EXTRA (Gen8+) upload, and shares a bit more code. This also simplifies the PMA stall code, making it match the formula more closely, and drops a BRW_NEW_FRAGMENT_PROGRAM dependency. (Note that the previous comment was wrong - the code and the documentation have != PSCDEPTH_OFF, not ==.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* freedreno/a4xx: unify vertex/texture formats into a single tableRob Clark2014-12-041-299/+180
| | | | | | Similar to the scheme that Ilia put in place for a3xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fd4_util -> fd4_formatRob Clark2014-12-0415-15/+15
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headers / a4xx fmt renameRob Clark2014-12-046-124/+124
| | | | Signed-off-by: Rob Clark <[email protected]>
* i965: Add var->location != -1 assertions.Kenneth Graunke2014-12-032-0/+3
| | | | | | | | | | We shouldn't receive variables with invalid locations set - adding these assertions should help catch problems before they cause crashes later. Inspired by similar code in st_glsl_to_tgsi. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Don't offset uniform registers in half().Matt Turner2014-12-031-0/+4
| | | | | | | Half gives you the second half of a SIMD16 register, but if the register is a uniform it would incorrectly give you the next register. Reviewed-by: Jason Ekstrand <[email protected]>
* freedreno/a4xx: frag-depth fixesRob Clark2014-12-032-18/+24
| | | | | | Also seems to fix kill/discard. Signed-off-by: Rob Clark <[email protected]>
* linker: Assign varying locations geometry shader inputs for SSOIan Romanick2014-12-031-0/+15
| | | | | | | | | | Previously only geometry shader outputs would be assigned locations if the geometry shader was the only stage in the linked program. Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585 Reviewed-by: Jordan Justen <[email protected]>
* linker: Wrap access of producer_var with a NULL checkIan Romanick2014-12-031-3/+5
| | | | | | | | | | | | producer_var could be NULL if consumer_var is not NULL and consumer_is_fs is false. This will occur when the producer is NULL and the consumer is the geometry shader for a program that contains only a geometry shader. This will occur starting with the next patch. Signed-off-by: Ian Romanick <[email protected]> Cc: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82585 Reviewed-by: Jordan Justen <[email protected]>
* st/xvmc: Fix compiler warningsJan Vesely2014-12-033-6/+6
| | | | | | | Mostly signed/unsigned comparison Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/nine: Fix vertex declarations for non-standard (usage/index)Axel Davy2014-12-037-108/+89
| | | | | | | | | | | | | | | | | | | | Nine code to match vertex declaration to vs inputs was limiting the number of possible combinations. Some sm3 games have issues with that, because arbitrary (usage/index) can be used. This patch does the following changes to fix the problem: . Change the numbers given to (usage/index) combinations to uint16 . Do not put limits on the indices when it doesn't make sense . change the conversion rule (usage/index) -> number to fit all combinations . Instead of having a table usage_map mapping a (usage/index) number to an input index, usage_map maps input indices to their (usage/index) Cc: "10.4" <[email protected]> Tested-by: Yaroslav Andrusyak <[email protected]> Acked-by: Ilia Mirkin <[email protected]> Signed-off-by: Axel Davy <[email protected]>
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